/*
 * Copyright (c) 2014, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
#ifndef __HW_SIM_REGISTERS_H__
#define __HW_SIM_REGISTERS_H__

#include "MK70F12.h"
#include "fsl_bitband.h"

/*
 * MK70F12 SIM
 *
 * System Integration Module
 *
 * Registers defined in this header file:
 * - HW_SIM_SOPT1 - System Options Register 1
 * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
 * - HW_SIM_SOPT2 - System Options Register 2
 * - HW_SIM_SOPT4 - System Options Register 4
 * - HW_SIM_SOPT5 - System Options Register 5
 * - HW_SIM_SOPT6 - System Options Register 6
 * - HW_SIM_SOPT7 - System Options Register 7
 * - HW_SIM_SDID - System Device Identification Register
 * - HW_SIM_SCGC1 - System Clock Gating Control Register 1
 * - HW_SIM_SCGC2 - System Clock Gating Control Register 2
 * - HW_SIM_SCGC3 - System Clock Gating Control Register 3
 * - HW_SIM_SCGC4 - System Clock Gating Control Register 4
 * - HW_SIM_SCGC5 - System Clock Gating Control Register 5
 * - HW_SIM_SCGC6 - System Clock Gating Control Register 6
 * - HW_SIM_SCGC7 - System Clock Gating Control Register 7
 * - HW_SIM_CLKDIV1 - System Clock Divider Register 1
 * - HW_SIM_CLKDIV2 - System Clock Divider Register 2
 * - HW_SIM_FCFG1 - Flash Configuration Register 1
 * - HW_SIM_FCFG2 - Flash Configuration Register 2
 * - HW_SIM_UIDH - Unique Identification Register High
 * - HW_SIM_UIDMH - Unique Identification Register Mid-High
 * - HW_SIM_UIDML - Unique Identification Register Mid Low
 * - HW_SIM_UIDL - Unique Identification Register Low
 * - HW_SIM_CLKDIV3 - System Clock Divider Register 3
 * - HW_SIM_CLKDIV4 - System Clock Divider Register 4
 * - HW_SIM_MCR - Misc Control Register
 *
 * - hw_sim_t - Struct containing all module registers.
 */

#define HW_SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */

/*******************************************************************************
 * HW_SIM_SOPT1 - System Options Register 1
 ******************************************************************************/

/*!
 * @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
 *
 * Reset value: 0x80009000U
 *
 * The SOPT1 register is only reset on POR or LVD.
 */
typedef union _hw_sim_sopt1
{
    uint32_t U;
    struct _hw_sim_sopt1_bitfields
    {
        uint32_t RESERVED0 : 12;       /*!< [11:0]  */
        uint32_t RAMSIZE : 4;          /*!< [15:12] RAM size */
        uint32_t RESERVED1 : 3;        /*!< [18:16]  */
        uint32_t OSC32KSEL : 1;        /*!< [19] 32 kHz oscillator clock select */
        uint32_t RESERVED2 : 9;        /*!< [28:20]  */
        uint32_t USBVSTBY : 1;         /*!< [29] USB voltage regulator in standby
                                        * mode during VLPR or VLPW */
        uint32_t USBSSTBY : 1;         /*!< [30] USB voltage regulator in standby
                                        * mode during Stop, VLPS, LLS or VLLS */
        uint32_t USBREGEN : 1;         /*!< [31] USB voltage regulator enable */
    } B;
} hw_sim_sopt1_t;

/*!
 * @name Constants and macros for entire SIM_SOPT1 register
 */
/*@{*/
#define HW_SIM_SOPT1_ADDR(x)     ((x) + 0x0U)

#define HW_SIM_SOPT1(x)          (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR(x))
#define HW_SIM_SOPT1_RD(x)       (HW_SIM_SOPT1(x).U)
#define HW_SIM_SOPT1_WR(x, v)    (HW_SIM_SOPT1(x).U = (v))
#define HW_SIM_SOPT1_SET(x, v)   (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) |  (v)))
#define HW_SIM_SOPT1_CLR(x, v)   (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v)))
#define HW_SIM_SOPT1_TOG(x, v)   (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SOPT1 bitfields
 */

/*!
 * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
 *
 * This field specifies the amount of system RAM available on the device.
 *
 * Values:
 * - 0000 - Undefined
 * - 0001 - Undefined
 * - 0010 - Undefined
 * - 0011 - Undefined
 * - 0100 - Undefined
 * - 0101 - Undefined
 * - 0110 - Undefined
 * - 0111 - Undefined
 * - 1000 - Undefined
 * - 1001 - 128 KB
 * - 1010 - Undefined
 * - 1011 - Undefined
 * - 1100 - Undefined
 * - 1101 - Undefined
 * - 1110 - Undefined
 * - 1111 - Undefined
 */
/*@{*/
#define BP_SIM_SOPT1_RAMSIZE (12U)         /*!< Bit position for SIM_SOPT1_RAMSIZE. */
#define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /*!< Bit mask for SIM_SOPT1_RAMSIZE. */
#define BS_SIM_SOPT1_RAMSIZE (4U)          /*!< Bit field size in bits for SIM_SOPT1_RAMSIZE. */

/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
#define BR_SIM_SOPT1_RAMSIZE(x) (HW_SIM_SOPT1(x).B.RAMSIZE)
/*@}*/

/*!
 * @name Register SIM_SOPT1, field OSC32KSEL[19] (RW)
 *
 * Selects either the system oscillator or RTC oscillator as the 32 kHz clock
 * source (ERCLK32K). This bit is reset only for POR/LVD.
 *
 * Values:
 * - 0 - System oscillator (OSC32KCLK)
 * - 1 - RTC oscillator
 */
/*@{*/
#define BP_SIM_SOPT1_OSC32KSEL (19U)       /*!< Bit position for SIM_SOPT1_OSC32KSEL. */
#define BM_SIM_SOPT1_OSC32KSEL (0x00080000U) /*!< Bit mask for SIM_SOPT1_OSC32KSEL. */
#define BS_SIM_SOPT1_OSC32KSEL (1U)        /*!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. */

/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
#define BR_SIM_SOPT1_OSC32KSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_OSC32KSEL))

/*! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. */
#define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL)

/*! @brief Set the OSC32KSEL field to a new value. */
#define BW_SIM_SOPT1_OSC32KSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_OSC32KSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
 *
 * Controls whether the USB voltage regulator is placed in standby mode during
 * VLPR and VLPW modes. This bit can only be written when the SOPT1CFG[UVSWE] bit
 * is set.
 *
 * Values:
 * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
 * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
 */
/*@{*/
#define BP_SIM_SOPT1_USBVSTBY (29U)        /*!< Bit position for SIM_SOPT1_USBVSTBY. */
#define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /*!< Bit mask for SIM_SOPT1_USBVSTBY. */
#define BS_SIM_SOPT1_USBVSTBY (1U)         /*!< Bit field size in bits for SIM_SOPT1_USBVSTBY. */

/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
#define BR_SIM_SOPT1_USBVSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY))

/*! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. */
#define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY)

/*! @brief Set the USBVSTBY field to a new value. */
#define BW_SIM_SOPT1_USBVSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
 *
 * Controls whether the USB voltage regulator is placed in standby mode during
 * Stop, VLPS, LLS and VLLS modes. This bit can only be written when the
 * SOPT1CFG[USSWE] bit is set.
 *
 * Values:
 * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
 *     modes.
 * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
 */
/*@{*/
#define BP_SIM_SOPT1_USBSSTBY (30U)        /*!< Bit position for SIM_SOPT1_USBSSTBY. */
#define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /*!< Bit mask for SIM_SOPT1_USBSSTBY. */
#define BS_SIM_SOPT1_USBSSTBY (1U)         /*!< Bit field size in bits for SIM_SOPT1_USBSSTBY. */

/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
#define BR_SIM_SOPT1_USBSSTBY(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY))

/*! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. */
#define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY)

/*! @brief Set the USBSSTBY field to a new value. */
#define BW_SIM_SOPT1_USBSSTBY(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
 *
 * Controls whether the USB voltage regulator is enabled. This bit can only be
 * written when the SOPT1CFG[URWE] bit is set.
 *
 * Values:
 * - 0 - USB voltage regulator is disabled.
 * - 1 - USB voltage regulator is enabled
 */
/*@{*/
#define BP_SIM_SOPT1_USBREGEN (31U)        /*!< Bit position for SIM_SOPT1_USBREGEN. */
#define BM_SIM_SOPT1_USBREGEN (0x80000000U) /*!< Bit mask for SIM_SOPT1_USBREGEN. */
#define BS_SIM_SOPT1_USBREGEN (1U)         /*!< Bit field size in bits for SIM_SOPT1_USBREGEN. */

/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
#define BR_SIM_SOPT1_USBREGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN))

/*! @brief Format value for bitfield SIM_SOPT1_USBREGEN. */
#define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN)

/*! @brief Set the USBREGEN field to a new value. */
#define BW_SIM_SOPT1_USBREGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SOPT1CFG - SOPT1 Configuration Register
 ******************************************************************************/

/*!
 * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_sopt1cfg
{
    uint32_t U;
    struct _hw_sim_sopt1cfg_bitfields
    {
        uint32_t RESERVED0 : 24;       /*!< [23:0]  */
        uint32_t URWE : 1;             /*!< [24] USB voltage regulator enable write
                                        * enable */
        uint32_t UVSWE : 1;            /*!< [25] USB voltage regulator VLP standby write
                                        * enable */
        uint32_t USSWE : 1;            /*!< [26] USB voltage regulator stop standby
                                        * write enable */
        uint32_t RESERVED1 : 5;        /*!< [31:27]  */
    } B;
} hw_sim_sopt1cfg_t;

/*!
 * @name Constants and macros for entire SIM_SOPT1CFG register
 */
/*@{*/
#define HW_SIM_SOPT1CFG_ADDR(x)  ((x) + 0x4U)

#define HW_SIM_SOPT1CFG(x)       (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x))
#define HW_SIM_SOPT1CFG_RD(x)    (HW_SIM_SOPT1CFG(x).U)
#define HW_SIM_SOPT1CFG_WR(x, v) (HW_SIM_SOPT1CFG(x).U = (v))
#define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) |  (v)))
#define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v)))
#define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SOPT1CFG bitfields
 */

/*!
 * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
 *
 * Writing one to this bit allows the SOPT1[USBREGEN] bit to be written. This
 * register bit clears after a write to SOPT1[USBREGEN].
 *
 * Values:
 * - 0 - SOPT1[USBREGEN] cannot be written.
 * - 1 - SOPT1[USBREGEN] can be written.
 */
/*@{*/
#define BP_SIM_SOPT1CFG_URWE (24U)         /*!< Bit position for SIM_SOPT1CFG_URWE. */
#define BM_SIM_SOPT1CFG_URWE (0x01000000U) /*!< Bit mask for SIM_SOPT1CFG_URWE. */
#define BS_SIM_SOPT1CFG_URWE (1U)          /*!< Bit field size in bits for SIM_SOPT1CFG_URWE. */

/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
#define BR_SIM_SOPT1CFG_URWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE))

/*! @brief Format value for bitfield SIM_SOPT1CFG_URWE. */
#define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE)

/*! @brief Set the URWE field to a new value. */
#define BW_SIM_SOPT1CFG_URWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
 *
 * Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This
 * register bit clears after a write to SOPT1[USBVSTBY].
 *
 * Values:
 * - 0 - SOPT1[USBVSTBY] cannot be written.
 * - 1 - SOPT1[USBVSTBY] can be written.
 */
/*@{*/
#define BP_SIM_SOPT1CFG_UVSWE (25U)        /*!< Bit position for SIM_SOPT1CFG_UVSWE. */
#define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /*!< Bit mask for SIM_SOPT1CFG_UVSWE. */
#define BS_SIM_SOPT1CFG_UVSWE (1U)         /*!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. */

/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
#define BR_SIM_SOPT1CFG_UVSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE))

/*! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. */
#define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE)

/*! @brief Set the UVSWE field to a new value. */
#define BW_SIM_SOPT1CFG_UVSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
 *
 * Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This
 * register bit clears after a write to SOPT1[USBSSTBY].
 *
 * Values:
 * - 0 - SOPT1[USBSSTBY] cannot be written.
 * - 1 - SOPT1[USBSSTBY] can be written.
 */
/*@{*/
#define BP_SIM_SOPT1CFG_USSWE (26U)        /*!< Bit position for SIM_SOPT1CFG_USSWE. */
#define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /*!< Bit mask for SIM_SOPT1CFG_USSWE. */
#define BS_SIM_SOPT1CFG_USSWE (1U)         /*!< Bit field size in bits for SIM_SOPT1CFG_USSWE. */

/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
#define BR_SIM_SOPT1CFG_USSWE(x) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE))

/*! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. */
#define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE)

/*! @brief Set the USSWE field to a new value. */
#define BW_SIM_SOPT1CFG_USSWE(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SOPT2 - System Options Register 2
 ******************************************************************************/

/*!
 * @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
 *
 * Reset value: 0x44001004U
 */
typedef union _hw_sim_sopt2
{
    uint32_t U;
    struct _hw_sim_sopt2_bitfields
    {
        uint32_t RESERVED0 : 2;        /*!< [1:0]  */
        uint32_t USBHSRC : 2;          /*!< [3:2] USB HS clock source select */
        uint32_t RTCCLKOUTSEL : 1;     /*!< [4] RTC clock out select */
        uint32_t CLKOUTSEL : 3;        /*!< [7:5] Clock out select */
        uint32_t FBSL : 2;             /*!< [9:8] Flexbus security level */
        uint32_t RESERVED1 : 1;        /*!< [10]  */
        uint32_t CMTUARTPAD : 1;       /*!< [11] CMT/UART pad drive strength */
        uint32_t TRACECLKSEL : 1;      /*!< [12] Debug trace clock select */
        uint32_t RESERVED2 : 1;        /*!< [13]  */
        uint32_t LCDC_CLKSEL : 1;      /*!< [14] LCDC pixel clock select */
        uint32_t NFC_CLKSEL : 1;       /*!< [15] NFC Flash clock select */
        uint32_t PLLFLLSEL : 2;        /*!< [17:16] PLL/FLL clock select */
        uint32_t USBF_CLKSEL : 1;      /*!< [18] USB FS clock select */
        uint32_t RESERVED3 : 1;        /*!< [19]  */
        uint32_t TIMESRC : 2;          /*!< [21:20] Ethernet timestamp clock source
                                        * select */
        uint32_t USBFSRC : 2;          /*!< [23:22] USB FS clock source select */
        uint32_t RESERVED4 : 2;        /*!< [25:24]  */
        uint32_t LCDCSRC : 2;          /*!< [27:26] LCDC Pixel clock source select */
        uint32_t ESDHCSRC : 2;         /*!< [29:28] ESDHC perclk source select */
        uint32_t NFCSRC : 2;           /*!< [31:30] NFC Flash clock source select */
    } B;
} hw_sim_sopt2_t;

/*!
 * @name Constants and macros for entire SIM_SOPT2 register
 */
/*@{*/
#define HW_SIM_SOPT2_ADDR(x)     ((x) + 0x1004U)

#define HW_SIM_SOPT2(x)          (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR(x))
#define HW_SIM_SOPT2_RD(x)       (HW_SIM_SOPT2(x).U)
#define HW_SIM_SOPT2_WR(x, v)    (HW_SIM_SOPT2(x).U = (v))
#define HW_SIM_SOPT2_SET(x, v)   (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) |  (v)))
#define HW_SIM_SOPT2_CLR(x, v)   (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v)))
#define HW_SIM_SOPT2_TOG(x, v)   (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SOPT2 bitfields
 */

/*!
 * @name Register SIM_SOPT2, field USBHSRC[3:2] (RW)
 *
 * Selects the clock source before clock divider for the USB 60 MHz clock.
 *
 * Values:
 * - 00 - Bus clock
 * - 01 - MCGPLL0CLK
 * - 10 - MCGPLL1CLK
 * - 11 - OSC0ERCLK
 */
/*@{*/
#define BP_SIM_SOPT2_USBHSRC (2U)          /*!< Bit position for SIM_SOPT2_USBHSRC. */
#define BM_SIM_SOPT2_USBHSRC (0x0000000CU) /*!< Bit mask for SIM_SOPT2_USBHSRC. */
#define BS_SIM_SOPT2_USBHSRC (2U)          /*!< Bit field size in bits for SIM_SOPT2_USBHSRC. */

/*! @brief Read current value of the SIM_SOPT2_USBHSRC field. */
#define BR_SIM_SOPT2_USBHSRC(x) (HW_SIM_SOPT2(x).B.USBHSRC)

/*! @brief Format value for bitfield SIM_SOPT2_USBHSRC. */
#define BF_SIM_SOPT2_USBHSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBHSRC) & BM_SIM_SOPT2_USBHSRC)

/*! @brief Set the USBHSRC field to a new value. */
#define BW_SIM_SOPT2_USBHSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_USBHSRC) | BF_SIM_SOPT2_USBHSRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
 *
 * Selects either the RTC 32 kHz clock or the RTC 1 Hz clock for the clock to
 * the RTC CLKOUT pin (PTE26). PTE26 must be configured for the RTC CLKOUT function.
 *
 * Values:
 * - 0 - RTC 1 Hz clock drives RTC CLKOUT.
 * - 1 - RTC 32 kHz oscillator drives RTC CLKOUT.
 */
/*@{*/
#define BP_SIM_SOPT2_RTCCLKOUTSEL (4U)     /*!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. */
#define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /*!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. */
#define BS_SIM_SOPT2_RTCCLKOUTSEL (1U)     /*!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. */

/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
#define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL))

/*! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. */
#define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL)

/*! @brief Set the RTCCLKOUTSEL field to a new value. */
#define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
 *
 * Selects what internal clock to output on CLKOUT pin.
 *
 * Values:
 * - 000 - FlexBus clock (reset value)
 * - 001 - Reserved
 * - 010 - Flash ungated clock
 * - 011 - LPO clock (1 kHz)
 * - 100 - MCGIRCLK
 * - 101 - RTC 32 kHz clock
 * - 110 - OSC0ERCLK
 * - 111 - OSC1ERCLK
 */
/*@{*/
#define BP_SIM_SOPT2_CLKOUTSEL (5U)        /*!< Bit position for SIM_SOPT2_CLKOUTSEL. */
#define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /*!< Bit mask for SIM_SOPT2_CLKOUTSEL. */
#define BS_SIM_SOPT2_CLKOUTSEL (3U)        /*!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. */

/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
#define BR_SIM_SOPT2_CLKOUTSEL(x) (HW_SIM_SOPT2(x).B.CLKOUTSEL)

/*! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. */
#define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL)

/*! @brief Set the CLKOUTSEL field to a new value. */
#define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
 *
 * If security is enabled, then this field affects what CPU operations can
 * access off-chip via the FlexBus interface. This field has no effect if security is
 * not enabled.
 *
 * Values:
 * - 00 - All off-chip accesses (op code and data) via the FlexBus are
 *     disallowed.
 * - 10 - Off-chip op code accesses are disallowed. Data accesses are allowed.
 * - 11 - Off-chip op code accesses and data accesses are allowed.
 */
/*@{*/
#define BP_SIM_SOPT2_FBSL    (8U)          /*!< Bit position for SIM_SOPT2_FBSL. */
#define BM_SIM_SOPT2_FBSL    (0x00000300U) /*!< Bit mask for SIM_SOPT2_FBSL. */
#define BS_SIM_SOPT2_FBSL    (2U)          /*!< Bit field size in bits for SIM_SOPT2_FBSL. */

/*! @brief Read current value of the SIM_SOPT2_FBSL field. */
#define BR_SIM_SOPT2_FBSL(x) (HW_SIM_SOPT2(x).B.FBSL)

/*! @brief Format value for bitfield SIM_SOPT2_FBSL. */
#define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL)

/*! @brief Set the FBSL field to a new value. */
#define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field CMTUARTPAD[11] (RW)
 *
 * Controls the output drive strength of the CMT IRO signal or UART0_TXD signal
 * on PTD7 pin by selecting either one or two pads to drive it.
 *
 * Values:
 * - 0 - Single-pad drive strength for CMT IRO or UART0_TXD.
 * - 1 - Dual-pad drive strength for CMT IRO or UART0_TXD.
 */
/*@{*/
#define BP_SIM_SOPT2_CMTUARTPAD (11U)      /*!< Bit position for SIM_SOPT2_CMTUARTPAD. */
#define BM_SIM_SOPT2_CMTUARTPAD (0x00000800U) /*!< Bit mask for SIM_SOPT2_CMTUARTPAD. */
#define BS_SIM_SOPT2_CMTUARTPAD (1U)       /*!< Bit field size in bits for SIM_SOPT2_CMTUARTPAD. */

/*! @brief Read current value of the SIM_SOPT2_CMTUARTPAD field. */
#define BR_SIM_SOPT2_CMTUARTPAD(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_CMTUARTPAD))

/*! @brief Format value for bitfield SIM_SOPT2_CMTUARTPAD. */
#define BF_SIM_SOPT2_CMTUARTPAD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CMTUARTPAD) & BM_SIM_SOPT2_CMTUARTPAD)

/*! @brief Set the CMTUARTPAD field to a new value. */
#define BW_SIM_SOPT2_CMTUARTPAD(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_CMTUARTPAD) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
 *
 * Selects either the core/system clock or PLL clock as the trace clock source.
 *
 * Values:
 * - 0 - MCGCLKOUT
 * - 1 - Core/system clock
 */
/*@{*/
#define BP_SIM_SOPT2_TRACECLKSEL (12U)     /*!< Bit position for SIM_SOPT2_TRACECLKSEL. */
#define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /*!< Bit mask for SIM_SOPT2_TRACECLKSEL. */
#define BS_SIM_SOPT2_TRACECLKSEL (1U)      /*!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. */

/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
#define BR_SIM_SOPT2_TRACECLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL))

/*! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. */
#define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL)

/*! @brief Set the TRACECLKSEL field to a new value. */
#define BW_SIM_SOPT2_TRACECLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field LCDC_CLKSEL[14] (RW)
 *
 * Values:
 * - 0 - Clock divider LCDC pixel clock
 * - 1 - EXTAL1 clock.
 */
/*@{*/
#define BP_SIM_SOPT2_LCDC_CLKSEL (14U)     /*!< Bit position for SIM_SOPT2_LCDC_CLKSEL. */
#define BM_SIM_SOPT2_LCDC_CLKSEL (0x00004000U) /*!< Bit mask for SIM_SOPT2_LCDC_CLKSEL. */
#define BS_SIM_SOPT2_LCDC_CLKSEL (1U)      /*!< Bit field size in bits for SIM_SOPT2_LCDC_CLKSEL. */

/*! @brief Read current value of the SIM_SOPT2_LCDC_CLKSEL field. */
#define BR_SIM_SOPT2_LCDC_CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_LCDC_CLKSEL))

/*! @brief Format value for bitfield SIM_SOPT2_LCDC_CLKSEL. */
#define BF_SIM_SOPT2_LCDC_CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_LCDC_CLKSEL) & BM_SIM_SOPT2_LCDC_CLKSEL)

/*! @brief Set the LCDC_CLKSEL field to a new value. */
#define BW_SIM_SOPT2_LCDC_CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_LCDC_CLKSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field NFC_CLKSEL[15] (RW)
 *
 * Values:
 * - 0 - Clock divider NFC clock
 * - 1 - EXTAL1 clock.
 */
/*@{*/
#define BP_SIM_SOPT2_NFC_CLKSEL (15U)      /*!< Bit position for SIM_SOPT2_NFC_CLKSEL. */
#define BM_SIM_SOPT2_NFC_CLKSEL (0x00008000U) /*!< Bit mask for SIM_SOPT2_NFC_CLKSEL. */
#define BS_SIM_SOPT2_NFC_CLKSEL (1U)       /*!< Bit field size in bits for SIM_SOPT2_NFC_CLKSEL. */

/*! @brief Read current value of the SIM_SOPT2_NFC_CLKSEL field. */
#define BR_SIM_SOPT2_NFC_CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_NFC_CLKSEL))

/*! @brief Format value for bitfield SIM_SOPT2_NFC_CLKSEL. */
#define BF_SIM_SOPT2_NFC_CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_NFC_CLKSEL) & BM_SIM_SOPT2_NFC_CLKSEL)

/*! @brief Set the NFC_CLKSEL field to a new value. */
#define BW_SIM_SOPT2_NFC_CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_NFC_CLKSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
 *
 * Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking
 * options.
 *
 * Values:
 * - 00 - MCGFLLCLK
 * - 01 - MCGPLL0CLK
 * - 10 - MCGPLL1CLK
 * - 11 - System Platform clock
 */
/*@{*/
#define BP_SIM_SOPT2_PLLFLLSEL (16U)       /*!< Bit position for SIM_SOPT2_PLLFLLSEL. */
#define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /*!< Bit mask for SIM_SOPT2_PLLFLLSEL. */
#define BS_SIM_SOPT2_PLLFLLSEL (2U)        /*!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. */

/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
#define BR_SIM_SOPT2_PLLFLLSEL(x) (HW_SIM_SOPT2(x).B.PLLFLLSEL)

/*! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. */
#define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL)

/*! @brief Set the PLLFLLSEL field to a new value. */
#define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field USBF_CLKSEL[18] (RW)
 *
 * Selects clock diver output or bypass clock.
 *
 * Values:
 * - 0 - External bypass clock (PTE26)
 * - 1 - Clock divider USB FS clock
 */
/*@{*/
#define BP_SIM_SOPT2_USBF_CLKSEL (18U)     /*!< Bit position for SIM_SOPT2_USBF_CLKSEL. */
#define BM_SIM_SOPT2_USBF_CLKSEL (0x00040000U) /*!< Bit mask for SIM_SOPT2_USBF_CLKSEL. */
#define BS_SIM_SOPT2_USBF_CLKSEL (1U)      /*!< Bit field size in bits for SIM_SOPT2_USBF_CLKSEL. */

/*! @brief Read current value of the SIM_SOPT2_USBF_CLKSEL field. */
#define BR_SIM_SOPT2_USBF_CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBF_CLKSEL))

/*! @brief Format value for bitfield SIM_SOPT2_USBF_CLKSEL. */
#define BF_SIM_SOPT2_USBF_CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBF_CLKSEL) & BM_SIM_SOPT2_USBF_CLKSEL)

/*! @brief Set the USBF_CLKSEL field to a new value. */
#define BW_SIM_SOPT2_USBF_CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBF_CLKSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
 *
 * Selects the clock source for the Ethernet timestamp clock.
 *
 * Values:
 * - 00 - System platform clock
 * - 01 - MCGPLLCLK/MCGFLLCLK selected by PLLFLLSEL[1:0]
 * - 10 - OSC0ERCLK
 * - 11 - External bypass clock (PTE26)
 */
/*@{*/
#define BP_SIM_SOPT2_TIMESRC (20U)         /*!< Bit position for SIM_SOPT2_TIMESRC. */
#define BM_SIM_SOPT2_TIMESRC (0x00300000U) /*!< Bit mask for SIM_SOPT2_TIMESRC. */
#define BS_SIM_SOPT2_TIMESRC (2U)          /*!< Bit field size in bits for SIM_SOPT2_TIMESRC. */

/*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */
#define BR_SIM_SOPT2_TIMESRC(x) (HW_SIM_SOPT2(x).B.TIMESRC)

/*! @brief Format value for bitfield SIM_SOPT2_TIMESRC. */
#define BF_SIM_SOPT2_TIMESRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TIMESRC) & BM_SIM_SOPT2_TIMESRC)

/*! @brief Set the TIMESRC field to a new value. */
#define BW_SIM_SOPT2_TIMESRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field USBFSRC[23:22] (RW)
 *
 * Selects the clock source for the USB 48 MHz clock.
 *
 * Values:
 * - 00 - MCGPLLCLK/MCGFLLCLK selected by PLLFLLSEL[1:0]
 * - 01 - MCGPLL0CLK
 * - 10 - MCGPLL1CLK
 * - 11 - OSC0ERCLK
 */
/*@{*/
#define BP_SIM_SOPT2_USBFSRC (22U)         /*!< Bit position for SIM_SOPT2_USBFSRC. */
#define BM_SIM_SOPT2_USBFSRC (0x00C00000U) /*!< Bit mask for SIM_SOPT2_USBFSRC. */
#define BS_SIM_SOPT2_USBFSRC (2U)          /*!< Bit field size in bits for SIM_SOPT2_USBFSRC. */

/*! @brief Read current value of the SIM_SOPT2_USBFSRC field. */
#define BR_SIM_SOPT2_USBFSRC(x) (HW_SIM_SOPT2(x).B.USBFSRC)

/*! @brief Format value for bitfield SIM_SOPT2_USBFSRC. */
#define BF_SIM_SOPT2_USBFSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBFSRC) & BM_SIM_SOPT2_USBFSRC)

/*! @brief Set the USBFSRC field to a new value. */
#define BW_SIM_SOPT2_USBFSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_USBFSRC) | BF_SIM_SOPT2_USBFSRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field LCDCSRC[27:26] (RW)
 *
 * Selects the clock source for LCDC pixel clock.
 *
 * Values:
 * - 00 - Bus clock
 * - 01 - MCGPLL0CLK
 * - 10 - MCGPLL1CLK
 * - 11 - OSC0ERCLK
 */
/*@{*/
#define BP_SIM_SOPT2_LCDCSRC (26U)         /*!< Bit position for SIM_SOPT2_LCDCSRC. */
#define BM_SIM_SOPT2_LCDCSRC (0x0C000000U) /*!< Bit mask for SIM_SOPT2_LCDCSRC. */
#define BS_SIM_SOPT2_LCDCSRC (2U)          /*!< Bit field size in bits for SIM_SOPT2_LCDCSRC. */

/*! @brief Read current value of the SIM_SOPT2_LCDCSRC field. */
#define BR_SIM_SOPT2_LCDCSRC(x) (HW_SIM_SOPT2(x).B.LCDCSRC)

/*! @brief Format value for bitfield SIM_SOPT2_LCDCSRC. */
#define BF_SIM_SOPT2_LCDCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_LCDCSRC) & BM_SIM_SOPT2_LCDCSRC)

/*! @brief Set the LCDCSRC field to a new value. */
#define BW_SIM_SOPT2_LCDCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_LCDCSRC) | BF_SIM_SOPT2_LCDCSRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field ESDHCSRC[29:28] (RW)
 *
 * Selects the clock source for the ESDHC clock .
 *
 * Values:
 * - 00 - Core/system clock
 * - 01 - MCGPLLCLK/MCGFLLCLK selected by PLLFLLSEL[1:0]
 * - 10 - OSC0ERCLK
 * - 11 - External bypass clock (PTD11)
 */
/*@{*/
#define BP_SIM_SOPT2_ESDHCSRC (28U)        /*!< Bit position for SIM_SOPT2_ESDHCSRC. */
#define BM_SIM_SOPT2_ESDHCSRC (0x30000000U) /*!< Bit mask for SIM_SOPT2_ESDHCSRC. */
#define BS_SIM_SOPT2_ESDHCSRC (2U)         /*!< Bit field size in bits for SIM_SOPT2_ESDHCSRC. */

/*! @brief Read current value of the SIM_SOPT2_ESDHCSRC field. */
#define BR_SIM_SOPT2_ESDHCSRC(x) (HW_SIM_SOPT2(x).B.ESDHCSRC)

/*! @brief Format value for bitfield SIM_SOPT2_ESDHCSRC. */
#define BF_SIM_SOPT2_ESDHCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_ESDHCSRC) & BM_SIM_SOPT2_ESDHCSRC)

/*! @brief Set the ESDHCSRC field to a new value. */
#define BW_SIM_SOPT2_ESDHCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_ESDHCSRC) | BF_SIM_SOPT2_ESDHCSRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT2, field NFCSRC[31:30] (RW)
 *
 * Selects the the clock divider source for NFC flash clock .
 *
 * Values:
 * - 00 - Bus clock
 * - 01 - MCGPLL0CLK
 * - 10 - MCGPLL1CLK
 * - 11 - OSC0ERCLK
 */
/*@{*/
#define BP_SIM_SOPT2_NFCSRC  (30U)         /*!< Bit position for SIM_SOPT2_NFCSRC. */
#define BM_SIM_SOPT2_NFCSRC  (0xC0000000U) /*!< Bit mask for SIM_SOPT2_NFCSRC. */
#define BS_SIM_SOPT2_NFCSRC  (2U)          /*!< Bit field size in bits for SIM_SOPT2_NFCSRC. */

/*! @brief Read current value of the SIM_SOPT2_NFCSRC field. */
#define BR_SIM_SOPT2_NFCSRC(x) (HW_SIM_SOPT2(x).B.NFCSRC)

/*! @brief Format value for bitfield SIM_SOPT2_NFCSRC. */
#define BF_SIM_SOPT2_NFCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_NFCSRC) & BM_SIM_SOPT2_NFCSRC)

/*! @brief Set the NFCSRC field to a new value. */
#define BW_SIM_SOPT2_NFCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_NFCSRC) | BF_SIM_SOPT2_NFCSRC(v)))
/*@}*/

/*******************************************************************************
 * HW_SIM_SOPT4 - System Options Register 4
 ******************************************************************************/

/*!
 * @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_sopt4
{
    uint32_t U;
    struct _hw_sim_sopt4_bitfields
    {
        uint32_t FTM0FLT0 : 1;         /*!< [0] FlexTimer 0 Fault 0 Select */
        uint32_t FTM0FLT1 : 1;         /*!< [1] FlexTimer 0 Fault 1 Select */
        uint32_t FTM0FLT2 : 1;         /*!< [2] FlexTimer 0 Fault 2 Select */
        uint32_t FTM0FLT3 : 1;         /*!< [3] FlexTimer 0 Fault 3 Select. */
        uint32_t FTM1FLT0 : 1;         /*!< [4] FlexTimer 1 Fault 0 Select */
        uint32_t RESERVED0 : 3;        /*!< [7:5]  */
        uint32_t FTM2FLT0 : 1;         /*!< [8] FlexTimer 2 Fault 0 Select */
        uint32_t RESERVED1 : 3;        /*!< [11:9]  */
        uint32_t FTM3FLT0 : 1;         /*!< [12] FlexTimer 3 Fault 0 Select. */
        uint32_t RESERVED2 : 5;        /*!< [17:13]  */
        uint32_t FTM1CH0SRC : 2;       /*!< [19:18] FlexTimer 1 channel 0 input
                                        * capture source select */
        uint32_t FTM2CH0SRC : 2;       /*!< [21:20] FlexTimer 2 channel 0 input
                                        * capture source select */
        uint32_t RESERVED3 : 2;        /*!< [23:22]  */
        uint32_t FTM0CLKSEL : 1;       /*!< [24] FlexTimer 0 external clock pin
                                        * select */
        uint32_t FTM1CLKSEL : 1;       /*!< [25] FlexTimer 1 external clock pin
                                        * select */
        uint32_t FTM2CLKSEL : 1;       /*!< [26] FlexTimer 2 external clock pin
                                        * select */
        uint32_t FTM3CLKSEL : 1;       /*!< [27] FlexTimer 3 external clock pin
                                        * select */
        uint32_t FTM0TRG0SRC : 1;      /*!< [28] FlexTimer 0 hardware trigger 0
                                        * source select */
        uint32_t FTM0TRG1SRC : 1;      /*!< [29] FlexTimer 0 hardware trigger 1
                                        * source select */
        uint32_t FTM3TRG0SRC : 1;      /*!< [30] FlexTimer 3 hardware trigger 0
                                        * source select */
        uint32_t FTM3TRG1SRC : 1;      /*!< [31] FlexTimer 3 hardware trigger 1
                                        * source select */
    } B;
} hw_sim_sopt4_t;

/*!
 * @name Constants and macros for entire SIM_SOPT4 register
 */
/*@{*/
#define HW_SIM_SOPT4_ADDR(x)     ((x) + 0x100CU)

#define HW_SIM_SOPT4(x)          (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR(x))
#define HW_SIM_SOPT4_RD(x)       (HW_SIM_SOPT4(x).U)
#define HW_SIM_SOPT4_WR(x, v)    (HW_SIM_SOPT4(x).U = (v))
#define HW_SIM_SOPT4_SET(x, v)   (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) |  (v)))
#define HW_SIM_SOPT4_CLR(x, v)   (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v)))
#define HW_SIM_SOPT4_TOG(x, v)   (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SOPT4 bitfields
 */

/*!
 * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
 *
 * Selects the source of FTM 0 fault 0. Note that the pin source for fault 0
 * must be configured for the FTM fault function through the appropriate PCTL pin
 * control register.
 *
 * Values:
 * - 0 - FTM0_FLT0 drives FTM 0 fault 0.
 * - 1 - CMP0 OUT drives FTM 0 fault 0.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM0FLT0 (0U)         /*!< Bit position for SIM_SOPT4_FTM0FLT0. */
#define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /*!< Bit mask for SIM_SOPT4_FTM0FLT0. */
#define BS_SIM_SOPT4_FTM0FLT0 (1U)         /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. */

/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
#define BR_SIM_SOPT4_FTM0FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0))

/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. */
#define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0)

/*! @brief Set the FTM0FLT0 field to a new value. */
#define BW_SIM_SOPT4_FTM0FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
 *
 * Selects the source of FTM 0 fault 1. Note that the pin source for fault 1
 * must be configured for the FTM fault function through the appropriate PCTL pin
 * control register.
 *
 * Values:
 * - 0 - FTM0_FLT1 drives FTM 0 fault 1.
 * - 1 - CMP1 OUT drives FTM 0 fault 1.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM0FLT1 (1U)         /*!< Bit position for SIM_SOPT4_FTM0FLT1. */
#define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /*!< Bit mask for SIM_SOPT4_FTM0FLT1. */
#define BS_SIM_SOPT4_FTM0FLT1 (1U)         /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. */

/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
#define BR_SIM_SOPT4_FTM0FLT1(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1))

/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. */
#define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1)

/*! @brief Set the FTM0FLT1 field to a new value. */
#define BW_SIM_SOPT4_FTM0FLT1(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
 *
 * Selects the source of FTM 0 fault 2. Note that the pin source for fault 2
 * must be configured for the FTM fault function through the appropriate PCTL pin
 * control register.
 *
 * Values:
 * - 0 - FTM0_FLT2 drives FTM 0 fault 2.
 * - 1 - CMP2 OUT drives FTM 0 fault 2.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM0FLT2 (2U)         /*!< Bit position for SIM_SOPT4_FTM0FLT2. */
#define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) /*!< Bit mask for SIM_SOPT4_FTM0FLT2. */
#define BS_SIM_SOPT4_FTM0FLT2 (1U)         /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT2. */

/*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */
#define BR_SIM_SOPT4_FTM0FLT2(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2))

/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2. */
#define BF_SIM_SOPT4_FTM0FLT2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT2) & BM_SIM_SOPT4_FTM0FLT2)

/*! @brief Set the FTM0FLT2 field to a new value. */
#define BW_SIM_SOPT4_FTM0FLT2(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM0FLT3[3] (RW)
 *
 * Selects the source of FTM 0 fault 3. Note that the pin source for fault 3
 * must be configured for the FTM fault function through the appropriate PCTL pin
 * control register.
 *
 * Values:
 * - 0 - FTM0_FLT3 drives FTM 0 fault 3.
 * - 1 - CMP0 OUT drives FTM 0 fault 3.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM0FLT3 (3U)         /*!< Bit position for SIM_SOPT4_FTM0FLT3. */
#define BM_SIM_SOPT4_FTM0FLT3 (0x00000008U) /*!< Bit mask for SIM_SOPT4_FTM0FLT3. */
#define BS_SIM_SOPT4_FTM0FLT3 (1U)         /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT3. */

/*! @brief Read current value of the SIM_SOPT4_FTM0FLT3 field. */
#define BR_SIM_SOPT4_FTM0FLT3(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT3))

/*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT3. */
#define BF_SIM_SOPT4_FTM0FLT3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT3) & BM_SIM_SOPT4_FTM0FLT3)

/*! @brief Set the FTM0FLT3 field to a new value. */
#define BW_SIM_SOPT4_FTM0FLT3(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT3) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
 *
 * Selects the source of FTM 1 fault 0. Note that the pin source for fault 0
 * must be configured for the FTM fault function through the appropriate PCTL pin
 * control register.
 *
 * Values:
 * - 0 - FTM1_FLT0 drives FTM 1 fault 0.
 * - 1 - CMP0 OUT drives FTM 1 fault 0.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM1FLT0 (4U)         /*!< Bit position for SIM_SOPT4_FTM1FLT0. */
#define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /*!< Bit mask for SIM_SOPT4_FTM1FLT0. */
#define BS_SIM_SOPT4_FTM1FLT0 (1U)         /*!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. */

/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
#define BR_SIM_SOPT4_FTM1FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0))

/*! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. */
#define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0)

/*! @brief Set the FTM1FLT0 field to a new value. */
#define BW_SIM_SOPT4_FTM1FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
 *
 * Selects the source of FTM 2 fault 0. Note that the pin source for fault 0
 * must be configured for the FTM fault function through the appropriate PCTL pin
 * control register.
 *
 * Values:
 * - 0 - FTM2_FLT0 drives FTM 2 fault 0.
 * - 1 - CMP0 OUT drives FTM 2 fault 0.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM2FLT0 (8U)         /*!< Bit position for SIM_SOPT4_FTM2FLT0. */
#define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /*!< Bit mask for SIM_SOPT4_FTM2FLT0. */
#define BS_SIM_SOPT4_FTM2FLT0 (1U)         /*!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. */

/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
#define BR_SIM_SOPT4_FTM2FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0))

/*! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. */
#define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0)

/*! @brief Set the FTM2FLT0 field to a new value. */
#define BW_SIM_SOPT4_FTM2FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
 *
 * Selects the source of FTM 3 fault 0. Note that the pin source for fault 0
 * must be configured for the FTM fault function through the appropriate PCTL pin
 * control register.
 *
 * Values:
 * - 0 - FTM3_FLT0 drives FTM 2 fault 0.
 * - 1 - CMP0 OUT drives FTM 2 fault 0.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM3FLT0 (12U)        /*!< Bit position for SIM_SOPT4_FTM3FLT0. */
#define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /*!< Bit mask for SIM_SOPT4_FTM3FLT0. */
#define BS_SIM_SOPT4_FTM3FLT0 (1U)         /*!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. */

/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
#define BR_SIM_SOPT4_FTM3FLT0(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0))

/*! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. */
#define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0)

/*! @brief Set the FTM3FLT0 field to a new value. */
#define BW_SIM_SOPT4_FTM3FLT0(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
 *
 * Selects the source for FTM 1 channel 0 input capture.
 *
 * Values:
 * - 00 - FTM1_CH0 pin
 * - 01 - CMP0 output
 * - 10 - CMP1 output
 * - 11 - USB SOF trigger
 */
/*@{*/
#define BP_SIM_SOPT4_FTM1CH0SRC (18U)      /*!< Bit position for SIM_SOPT4_FTM1CH0SRC. */
#define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /*!< Bit mask for SIM_SOPT4_FTM1CH0SRC. */
#define BS_SIM_SOPT4_FTM1CH0SRC (2U)       /*!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. */

/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
#define BR_SIM_SOPT4_FTM1CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM1CH0SRC)

/*! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. */
#define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC)

/*! @brief Set the FTM1CH0SRC field to a new value. */
#define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
 *
 * Selects the source for FTM 2 channel 0 input capture.
 *
 * Values:
 * - 00 - FTM2_CH0 pin
 * - 01 - CMP0 output
 * - 10 - CMP1 output
 * - 11 - Reserved
 */
/*@{*/
#define BP_SIM_SOPT4_FTM2CH0SRC (20U)      /*!< Bit position for SIM_SOPT4_FTM2CH0SRC. */
#define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /*!< Bit mask for SIM_SOPT4_FTM2CH0SRC. */
#define BS_SIM_SOPT4_FTM2CH0SRC (2U)       /*!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. */

/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
#define BR_SIM_SOPT4_FTM2CH0SRC(x) (HW_SIM_SOPT4(x).B.FTM2CH0SRC)

/*! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. */
#define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC)

/*! @brief Set the FTM2CH0SRC field to a new value. */
#define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
 *
 * Selects the external pin used to drive the external clock to the FTM0 module.
 * Note that the selected pin must also be configured for the FTM external clock
 * function through the appropriate PCTL pin control register.
 *
 * Values:
 * - 0 - FTM0 external clock driven by FTM CLKIN0 pin
 * - 1 - FTM0 external clock driven by FTM CLKIN1 pin.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM0CLKSEL (24U)      /*!< Bit position for SIM_SOPT4_FTM0CLKSEL. */
#define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /*!< Bit mask for SIM_SOPT4_FTM0CLKSEL. */
#define BS_SIM_SOPT4_FTM0CLKSEL (1U)       /*!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. */

/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
#define BR_SIM_SOPT4_FTM0CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL))

/*! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. */
#define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL)

/*! @brief Set the FTM0CLKSEL field to a new value. */
#define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
 *
 * Selects the external pin used to drive the external clock to the FTM1 module.
 * Note that the selected pin must also be configured for the FTM external clock
 * function through the appropriate PCTL pin control register.
 *
 * Values:
 * - 0 - FTM1 external clock driven by FTM CLKIN0 pin.
 * - 1 - FTM1 external clock driven by FTM CLKIN1 pin.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM1CLKSEL (25U)      /*!< Bit position for SIM_SOPT4_FTM1CLKSEL. */
#define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /*!< Bit mask for SIM_SOPT4_FTM1CLKSEL. */
#define BS_SIM_SOPT4_FTM1CLKSEL (1U)       /*!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. */

/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
#define BR_SIM_SOPT4_FTM1CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL))

/*! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. */
#define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL)

/*! @brief Set the FTM1CLKSEL field to a new value. */
#define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
 *
 * Selects the external pin used to drive the external clock to the FTM2 module.
 * Note that the selected pin must also be configured for the FTM external clock
 * function through the appropriate PCTL pin control register.
 *
 * Values:
 * - 0 - FTM2 external clock driven by FTM CLKIN0 pin.
 * - 1 - FTM2 external clock driven by FTM CLKIN1 pin.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM2CLKSEL (26U)      /*!< Bit position for SIM_SOPT4_FTM2CLKSEL. */
#define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /*!< Bit mask for SIM_SOPT4_FTM2CLKSEL. */
#define BS_SIM_SOPT4_FTM2CLKSEL (1U)       /*!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. */

/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
#define BR_SIM_SOPT4_FTM2CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL))

/*! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. */
#define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL)

/*! @brief Set the FTM2CLKSEL field to a new value. */
#define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
 *
 * Selects the external pin used to drive the external clock to the FTM 3
 * module. Note that the selected pin must also be configured for the FTM external
 * clock function through the appropriate PCTL pin control register.
 *
 * Values:
 * - 0 - FTM3 external clock driven by FTM CLKIN0 pin.
 * - 1 - FTM3 external clock driven by FTM CLKIN1 pin .
 */
/*@{*/
#define BP_SIM_SOPT4_FTM3CLKSEL (27U)      /*!< Bit position for SIM_SOPT4_FTM3CLKSEL. */
#define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /*!< Bit mask for SIM_SOPT4_FTM3CLKSEL. */
#define BS_SIM_SOPT4_FTM3CLKSEL (1U)       /*!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. */

/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
#define BR_SIM_SOPT4_FTM3CLKSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL))

/*! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. */
#define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL)

/*! @brief Set the FTM3CLKSEL field to a new value. */
#define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
 *
 * Selects the source of FTM0 hardware trigger 0.
 *
 * Values:
 * - 0 - CMP0 OUT drives FTM0 hardware trigger 0.
 * - 1 - FTM1 channel match trigger drives FTM0 hardware trigger 0.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM0TRG0SRC (28U)     /*!< Bit position for SIM_SOPT4_FTM0TRG0SRC. */
#define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. */
#define BS_SIM_SOPT4_FTM0TRG0SRC (1U)      /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. */

/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
#define BR_SIM_SOPT4_FTM0TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC))

/*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. */
#define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC)

/*! @brief Set the FTM0TRG0SRC field to a new value. */
#define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
 *
 * Selects the source of FTM0 hardware trigger 1.
 *
 * Values:
 * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1.
 * - 1 - FTM2 channel match trigger drives FTM0 hardware trigger 1.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM0TRG1SRC (29U)     /*!< Bit position for SIM_SOPT4_FTM0TRG1SRC. */
#define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. */
#define BS_SIM_SOPT4_FTM0TRG1SRC (1U)      /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. */

/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
#define BR_SIM_SOPT4_FTM0TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC))

/*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. */
#define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC)

/*! @brief Set the FTM0TRG1SRC field to a new value. */
#define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
 *
 * Selects the source of FTM3 hardware trigger 0.
 *
 * Values:
 * - 0 - CMP3 OUT drives FTM3 hardware trigger 0.
 * - 1 - FTM1 channel match trigger drives FTM3 hardware trigger 0.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM3TRG0SRC (30U)     /*!< Bit position for SIM_SOPT4_FTM3TRG0SRC. */
#define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. */
#define BS_SIM_SOPT4_FTM3TRG0SRC (1U)      /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. */

/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
#define BR_SIM_SOPT4_FTM3TRG0SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC))

/*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. */
#define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC)

/*! @brief Set the FTM3TRG0SRC field to a new value. */
#define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
 *
 * Selects the source of FTM3 hardware trigger 1.
 *
 * Values:
 * - 0 - PDB output trigger 3 drives FTM3 hardware trigger 1.
 * - 1 - FTM2 channel match trigger drives FTM3 hardware trigger 1.
 */
/*@{*/
#define BP_SIM_SOPT4_FTM3TRG1SRC (31U)     /*!< Bit position for SIM_SOPT4_FTM3TRG1SRC. */
#define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. */
#define BS_SIM_SOPT4_FTM3TRG1SRC (1U)      /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. */

/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
#define BR_SIM_SOPT4_FTM3TRG1SRC(x) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC))

/*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. */
#define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC)

/*! @brief Set the FTM3TRG1SRC field to a new value. */
#define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SOPT5 - System Options Register 5
 ******************************************************************************/

/*!
 * @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_sopt5
{
    uint32_t U;
    struct _hw_sim_sopt5_bitfields
    {
        uint32_t UART0TXSRC : 2;       /*!< [1:0] UART0 transmit data source select
                                        * */
        uint32_t UART0RXSRC : 2;       /*!< [3:2] UART0 receive data source select
                                        * */
        uint32_t UART1TXSRC : 2;       /*!< [5:4] UART1 transmit data source select
                                        * */
        uint32_t UART1RXSRC : 2;       /*!< [7:6] UART1 receive data source select
                                        * */
        uint32_t RESERVED0 : 24;       /*!< [31:8]  */
    } B;
} hw_sim_sopt5_t;

/*!
 * @name Constants and macros for entire SIM_SOPT5 register
 */
/*@{*/
#define HW_SIM_SOPT5_ADDR(x)     ((x) + 0x1010U)

#define HW_SIM_SOPT5(x)          (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR(x))
#define HW_SIM_SOPT5_RD(x)       (HW_SIM_SOPT5(x).U)
#define HW_SIM_SOPT5_WR(x, v)    (HW_SIM_SOPT5(x).U = (v))
#define HW_SIM_SOPT5_SET(x, v)   (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) |  (v)))
#define HW_SIM_SOPT5_CLR(x, v)   (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v)))
#define HW_SIM_SOPT5_TOG(x, v)   (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SOPT5 bitfields
 */

/*!
 * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
 *
 * Selects the source for the UART0 transmit data.
 *
 * Values:
 * - 00 - UART0_TX pin
 * - 01 - UART0_TX pin modulated with FTM1 channel 0 output
 * - 10 - UART0_TX pin modulated with FTM2 channel 0 output
 * - 11 - Reserved
 */
/*@{*/
#define BP_SIM_SOPT5_UART0TXSRC (0U)       /*!< Bit position for SIM_SOPT5_UART0TXSRC. */
#define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /*!< Bit mask for SIM_SOPT5_UART0TXSRC. */
#define BS_SIM_SOPT5_UART0TXSRC (2U)       /*!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. */

/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
#define BR_SIM_SOPT5_UART0TXSRC(x) (HW_SIM_SOPT5(x).B.UART0TXSRC)

/*! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. */
#define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC)

/*! @brief Set the UART0TXSRC field to a new value. */
#define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
 *
 * Selects the source for the UART0 receive data.
 *
 * Values:
 * - 00 - UART0_RX pin
 * - 01 - CMP0
 * - 10 - CMP1
 * - 11 - Reserved
 */
/*@{*/
#define BP_SIM_SOPT5_UART0RXSRC (2U)       /*!< Bit position for SIM_SOPT5_UART0RXSRC. */
#define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /*!< Bit mask for SIM_SOPT5_UART0RXSRC. */
#define BS_SIM_SOPT5_UART0RXSRC (2U)       /*!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. */

/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
#define BR_SIM_SOPT5_UART0RXSRC(x) (HW_SIM_SOPT5(x).B.UART0RXSRC)

/*! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. */
#define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC)

/*! @brief Set the UART0RXSRC field to a new value. */
#define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
 *
 * Selects the source for the UART1 transmit data.
 *
 * Values:
 * - 00 - UART1_TX pin
 * - 01 - UART1_TX pin modulated with FTM1 channel 0 Output
 * - 10 - UART1_TX pin modulated with FTM2 channel 0 Output
 * - 11 - Reserved
 */
/*@{*/
#define BP_SIM_SOPT5_UART1TXSRC (4U)       /*!< Bit position for SIM_SOPT5_UART1TXSRC. */
#define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /*!< Bit mask for SIM_SOPT5_UART1TXSRC. */
#define BS_SIM_SOPT5_UART1TXSRC (2U)       /*!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. */

/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
#define BR_SIM_SOPT5_UART1TXSRC(x) (HW_SIM_SOPT5(x).B.UART1TXSRC)

/*! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. */
#define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC)

/*! @brief Set the UART1TXSRC field to a new value. */
#define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
 *
 * Selects the source for the UART1 receive data.
 *
 * Values:
 * - 00 - UART1_RX pin
 * - 01 - CMP0
 * - 10 - CMP1
 * - 11 - Reserved
 */
/*@{*/
#define BP_SIM_SOPT5_UART1RXSRC (6U)       /*!< Bit position for SIM_SOPT5_UART1RXSRC. */
#define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /*!< Bit mask for SIM_SOPT5_UART1RXSRC. */
#define BS_SIM_SOPT5_UART1RXSRC (2U)       /*!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. */

/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
#define BR_SIM_SOPT5_UART1RXSRC(x) (HW_SIM_SOPT5(x).B.UART1RXSRC)

/*! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. */
#define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC)

/*! @brief Set the UART1RXSRC field to a new value. */
#define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v)))
/*@}*/

/*******************************************************************************
 * HW_SIM_SOPT6 - System Options Register 6
 ******************************************************************************/

/*!
 * @brief HW_SIM_SOPT6 - System Options Register 6 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_sopt6
{
    uint32_t U;
    struct _hw_sim_sopt6_bitfields
    {
        uint32_t MCC : 16;             /*!< [15:0] MCC */
        uint32_t PCR : 4;              /*!< [19:16] PCR */
        uint32_t RESERVED0 : 12;       /*!< [31:20]  */
    } B;
} hw_sim_sopt6_t;

/*!
 * @name Constants and macros for entire SIM_SOPT6 register
 */
/*@{*/
#define HW_SIM_SOPT6_ADDR(x)     ((x) + 0x1014U)

#define HW_SIM_SOPT6(x)          (*(__IO hw_sim_sopt6_t *) HW_SIM_SOPT6_ADDR(x))
#define HW_SIM_SOPT6_RD(x)       (HW_SIM_SOPT6(x).U)
#define HW_SIM_SOPT6_WR(x, v)    (HW_SIM_SOPT6(x).U = (v))
#define HW_SIM_SOPT6_SET(x, v)   (HW_SIM_SOPT6_WR(x, HW_SIM_SOPT6_RD(x) |  (v)))
#define HW_SIM_SOPT6_CLR(x, v)   (HW_SIM_SOPT6_WR(x, HW_SIM_SOPT6_RD(x) & ~(v)))
#define HW_SIM_SOPT6_TOG(x, v)   (HW_SIM_SOPT6_WR(x, HW_SIM_SOPT6_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SOPT6 bitfields
 */

/*!
 * @name Register SIM_SOPT6, field MCC[15:0] (RW)
 *
 * NFC hold cycle in case FlexBus request while NFC is granted.
 */
/*@{*/
#define BP_SIM_SOPT6_MCC     (0U)          /*!< Bit position for SIM_SOPT6_MCC. */
#define BM_SIM_SOPT6_MCC     (0x0000FFFFU) /*!< Bit mask for SIM_SOPT6_MCC. */
#define BS_SIM_SOPT6_MCC     (16U)         /*!< Bit field size in bits for SIM_SOPT6_MCC. */

/*! @brief Read current value of the SIM_SOPT6_MCC field. */
#define BR_SIM_SOPT6_MCC(x)  (HW_SIM_SOPT6(x).B.MCC)

/*! @brief Format value for bitfield SIM_SOPT6_MCC. */
#define BF_SIM_SOPT6_MCC(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT6_MCC) & BM_SIM_SOPT6_MCC)

/*! @brief Set the MCC field to a new value. */
#define BW_SIM_SOPT6_MCC(x, v) (HW_SIM_SOPT6_WR(x, (HW_SIM_SOPT6_RD(x) & ~BM_SIM_SOPT6_MCC) | BF_SIM_SOPT6_MCC(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT6, field PCR[19:16] (RW)
 *
 * FlexBus hold cycles before FlexBus can release bus to NFC or to IDLE.
 */
/*@{*/
#define BP_SIM_SOPT6_PCR     (16U)         /*!< Bit position for SIM_SOPT6_PCR. */
#define BM_SIM_SOPT6_PCR     (0x000F0000U) /*!< Bit mask for SIM_SOPT6_PCR. */
#define BS_SIM_SOPT6_PCR     (4U)          /*!< Bit field size in bits for SIM_SOPT6_PCR. */

/*! @brief Read current value of the SIM_SOPT6_PCR field. */
#define BR_SIM_SOPT6_PCR(x)  (HW_SIM_SOPT6(x).B.PCR)

/*! @brief Format value for bitfield SIM_SOPT6_PCR. */
#define BF_SIM_SOPT6_PCR(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT6_PCR) & BM_SIM_SOPT6_PCR)

/*! @brief Set the PCR field to a new value. */
#define BW_SIM_SOPT6_PCR(x, v) (HW_SIM_SOPT6_WR(x, (HW_SIM_SOPT6_RD(x) & ~BM_SIM_SOPT6_PCR) | BF_SIM_SOPT6_PCR(v)))
/*@}*/

/*******************************************************************************
 * HW_SIM_SOPT7 - System Options Register 7
 ******************************************************************************/

/*!
 * @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_sopt7
{
    uint32_t U;
    struct _hw_sim_sopt7_bitfields
    {
        uint32_t ADC0TRGSEL : 4;       /*!< [3:0] ADC0 trigger select */
        uint32_t ADC0PRETRGSEL : 1;    /*!< [4] ADC0 pre-trigger select */
        uint32_t RESERVED0 : 2;        /*!< [6:5]  */
        uint32_t ADC0ALTTRGEN : 1;     /*!< [7] ADC0 alternate trigger enable */
        uint32_t ADC1TRGSEL : 4;       /*!< [11:8] ADC1 trigger select */
        uint32_t ADC1PRETRGSEL : 1;    /*!< [12] ADC1 pre-trigger select */
        uint32_t RESERVED1 : 2;        /*!< [14:13]  */
        uint32_t ADC1ALTTRGEN : 1;     /*!< [15] ADC1 alternate trigger enable */
        uint32_t ADC2TRGSEL : 4;       /*!< [19:16] ADC2 trigger select */
        uint32_t ADC2PRETRGSEL : 1;    /*!< [20] ADC2 pre-trigger select */
        uint32_t RESERVED2 : 2;        /*!< [22:21]  */
        uint32_t ADC2ALTTRGEN : 1;     /*!< [23] ADC2 alternate trigger enable */
        uint32_t ADC3TRGSEL : 4;       /*!< [27:24] ADC3 trigger select */
        uint32_t ADC3PRETRGSEL : 1;    /*!< [28] ADC3 pre-trigger select */
        uint32_t RESERVED3 : 2;        /*!< [30:29]  */
        uint32_t ADC3ALTTRGEN : 1;     /*!< [31] ADC3 alternate trigger enable */
    } B;
} hw_sim_sopt7_t;

/*!
 * @name Constants and macros for entire SIM_SOPT7 register
 */
/*@{*/
#define HW_SIM_SOPT7_ADDR(x)     ((x) + 0x1018U)

#define HW_SIM_SOPT7(x)          (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR(x))
#define HW_SIM_SOPT7_RD(x)       (HW_SIM_SOPT7(x).U)
#define HW_SIM_SOPT7_WR(x, v)    (HW_SIM_SOPT7(x).U = (v))
#define HW_SIM_SOPT7_SET(x, v)   (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) |  (v)))
#define HW_SIM_SOPT7_CLR(x, v)   (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v)))
#define HW_SIM_SOPT7_TOG(x, v)   (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SOPT7 bitfields
 */

/*!
 * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
 *
 * Selects the ADC0 trigger source when alternative triggers are enabled through
 * ADC0ALTTRGEN.
 *
 * Values:
 * - 0000 - External trigger
 * - 0001 - High speed comparator 0 asynchronous interrupt
 * - 0010 - High speed comparator 1 asynchronous interrupt
 * - 0011 - High speed comparator 2 asynchronous interrupt
 * - 0100 - PIT trigger 0
 * - 0101 - PIT trigger 1
 * - 0110 - PIT trigger 2
 * - 0111 - PIT trigger 3
 * - 1000 - FTM0 trigger
 * - 1001 - FTM1 trigger
 * - 1010 - FTM2 trigger
 * - 1011 - FTM3 trigger
 * - 1100 - RTC alarm
 * - 1101 - RTC seconds
 * - 1110 - Low-power timer trigger
 * - 1111 - High speed comparator 3 asynchronous interrupt
 */
/*@{*/
#define BP_SIM_SOPT7_ADC0TRGSEL (0U)       /*!< Bit position for SIM_SOPT7_ADC0TRGSEL. */
#define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /*!< Bit mask for SIM_SOPT7_ADC0TRGSEL. */
#define BS_SIM_SOPT7_ADC0TRGSEL (4U)       /*!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. */

/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
#define BR_SIM_SOPT7_ADC0TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC0TRGSEL)

/*! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. */
#define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL)

/*! @brief Set the ADC0TRGSEL field to a new value. */
#define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
 *
 * Selects the ADC0 pre-trigger source when alternative triggers are enabled
 * through ADC0ALTTRGEN.
 *
 * Values:
 * - 0 - Pre-trigger A selected for ADC0.
 * - 1 - Pre-trigger B selected for ADC0.
 */
/*@{*/
#define BP_SIM_SOPT7_ADC0PRETRGSEL (4U)    /*!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. */
#define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /*!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. */
#define BS_SIM_SOPT7_ADC0PRETRGSEL (1U)    /*!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. */

/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
#define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL))

/*! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. */
#define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL)

/*! @brief Set the ADC0PRETRGSEL field to a new value. */
#define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
 *
 * Enable alternative conversion triggers for ADC0.
 *
 * Values:
 * - 0 - PDB trigger selected for ADC0.
 * - 1 - Alternate trigger selected for ADC0.
 */
/*@{*/
#define BP_SIM_SOPT7_ADC0ALTTRGEN (7U)     /*!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. */
#define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /*!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. */
#define BS_SIM_SOPT7_ADC0ALTTRGEN (1U)     /*!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. */

/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
#define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN))

/*! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. */
#define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN)

/*! @brief Set the ADC0ALTTRGEN field to a new value. */
#define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
 *
 * Selects the ADC1 trigger source when alternative triggers are enabled through
 * ADC1ALTTRGEN.
 *
 * Values:
 * - 0000 - External trigger
 * - 0001 - High speed comparator 0 asynchronous interrupt
 * - 0010 - High speed comparator 1 asynchronous interrupt
 * - 0011 - High speed comparator 2 asynchronous interrupt
 * - 0100 - PIT trigger 0
 * - 0101 - PIT trigger 1
 * - 0110 - PIT trigger 2
 * - 0111 - PIT trigger 3
 * - 1000 - FTM0 trigger
 * - 1001 - FTM1 trigger
 * - 1010 - FTM2 trigger
 * - 1011 - FTM3 trigger
 * - 1100 - RTC alarm
 * - 1101 - RTC seconds
 * - 1110 - Low-power timer trigger
 * - 1111 - High speed comparator 3 asynchronous interrupt
 */
/*@{*/
#define BP_SIM_SOPT7_ADC1TRGSEL (8U)       /*!< Bit position for SIM_SOPT7_ADC1TRGSEL. */
#define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /*!< Bit mask for SIM_SOPT7_ADC1TRGSEL. */
#define BS_SIM_SOPT7_ADC1TRGSEL (4U)       /*!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. */

/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
#define BR_SIM_SOPT7_ADC1TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC1TRGSEL)

/*! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. */
#define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL)

/*! @brief Set the ADC1TRGSEL field to a new value. */
#define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
 *
 * Selects the ADC1 pre-trigger source when alternative triggers are enabled
 * through ADC1ALTTRGEN.
 *
 * Values:
 * - 0 - Pre-trigger A selected for ADC1.
 * - 1 - Pre-trigger B selected for ADC1.
 */
/*@{*/
#define BP_SIM_SOPT7_ADC1PRETRGSEL (12U)   /*!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. */
#define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /*!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. */
#define BS_SIM_SOPT7_ADC1PRETRGSEL (1U)    /*!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. */

/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
#define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL))

/*! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. */
#define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL)

/*! @brief Set the ADC1PRETRGSEL field to a new value. */
#define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
 *
 * Enable alternative conversion triggers for ADC1.
 *
 * Values:
 * - 0 - PDB trigger selected for ADC1.
 * - 1 - Alternate trigger selected for ADC1.
 */
/*@{*/
#define BP_SIM_SOPT7_ADC1ALTTRGEN (15U)    /*!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. */
#define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /*!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. */
#define BS_SIM_SOPT7_ADC1ALTTRGEN (1U)     /*!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. */

/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
#define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN))

/*! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. */
#define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN)

/*! @brief Set the ADC1ALTTRGEN field to a new value. */
#define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC2TRGSEL[19:16] (RW)
 *
 * Selects the ADC2 trigger source when alternative triggers are enabled through
 * ADC2ALTTRGEN.
 *
 * Values:
 * - 0000 - External trigger
 * - 0001 - High speed comparator 0 asynchronous interrupt
 * - 0010 - High speed comparator 1 asynchronous interrupt
 * - 0011 - High speed comparator 2 asynchronous interrupt
 * - 0100 - PIT trigger 0
 * - 0101 - PIT trigger 1
 * - 0110 - PIT trigger 2
 * - 0111 - PIT trigger 3
 * - 1000 - FTM0 trigger
 * - 1001 - FTM1 trigger
 * - 1010 - FTM2 trigger
 * - 1011 - FTM3 trigger
 * - 1100 - RTC alarm
 * - 1101 - RTC seconds
 * - 1110 - Low-power timer trigger
 * - 1111 - High speed comparator 3 asynchronous interrupt
 */
/*@{*/
#define BP_SIM_SOPT7_ADC2TRGSEL (16U)      /*!< Bit position for SIM_SOPT7_ADC2TRGSEL. */
#define BM_SIM_SOPT7_ADC2TRGSEL (0x000F0000U) /*!< Bit mask for SIM_SOPT7_ADC2TRGSEL. */
#define BS_SIM_SOPT7_ADC2TRGSEL (4U)       /*!< Bit field size in bits for SIM_SOPT7_ADC2TRGSEL. */

/*! @brief Read current value of the SIM_SOPT7_ADC2TRGSEL field. */
#define BR_SIM_SOPT7_ADC2TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC2TRGSEL)

/*! @brief Format value for bitfield SIM_SOPT7_ADC2TRGSEL. */
#define BF_SIM_SOPT7_ADC2TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC2TRGSEL) & BM_SIM_SOPT7_ADC2TRGSEL)

/*! @brief Set the ADC2TRGSEL field to a new value. */
#define BW_SIM_SOPT7_ADC2TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC2TRGSEL) | BF_SIM_SOPT7_ADC2TRGSEL(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC2PRETRGSEL[20] (RW)
 *
 * Selects the ADC2 pre-trigger source when alternative triggers are enabled
 * through ADC2ALTTRGEN.
 *
 * Values:
 * - 0 - Pre-trigger A selected for ADC2.
 * - 1 - Pre-trigger B selected for ADC2.
 */
/*@{*/
#define BP_SIM_SOPT7_ADC2PRETRGSEL (20U)   /*!< Bit position for SIM_SOPT7_ADC2PRETRGSEL. */
#define BM_SIM_SOPT7_ADC2PRETRGSEL (0x00100000U) /*!< Bit mask for SIM_SOPT7_ADC2PRETRGSEL. */
#define BS_SIM_SOPT7_ADC2PRETRGSEL (1U)    /*!< Bit field size in bits for SIM_SOPT7_ADC2PRETRGSEL. */

/*! @brief Read current value of the SIM_SOPT7_ADC2PRETRGSEL field. */
#define BR_SIM_SOPT7_ADC2PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC2PRETRGSEL))

/*! @brief Format value for bitfield SIM_SOPT7_ADC2PRETRGSEL. */
#define BF_SIM_SOPT7_ADC2PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC2PRETRGSEL) & BM_SIM_SOPT7_ADC2PRETRGSEL)

/*! @brief Set the ADC2PRETRGSEL field to a new value. */
#define BW_SIM_SOPT7_ADC2PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC2PRETRGSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC2ALTTRGEN[23] (RW)
 *
 * Enable alternative conversion triggers for ADC2.
 *
 * Values:
 * - 0 - PDB trigger selected for ADC2.
 * - 1 - Alternate trigger selected for ADC2.
 */
/*@{*/
#define BP_SIM_SOPT7_ADC2ALTTRGEN (23U)    /*!< Bit position for SIM_SOPT7_ADC2ALTTRGEN. */
#define BM_SIM_SOPT7_ADC2ALTTRGEN (0x00800000U) /*!< Bit mask for SIM_SOPT7_ADC2ALTTRGEN. */
#define BS_SIM_SOPT7_ADC2ALTTRGEN (1U)     /*!< Bit field size in bits for SIM_SOPT7_ADC2ALTTRGEN. */

/*! @brief Read current value of the SIM_SOPT7_ADC2ALTTRGEN field. */
#define BR_SIM_SOPT7_ADC2ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC2ALTTRGEN))

/*! @brief Format value for bitfield SIM_SOPT7_ADC2ALTTRGEN. */
#define BF_SIM_SOPT7_ADC2ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC2ALTTRGEN) & BM_SIM_SOPT7_ADC2ALTTRGEN)

/*! @brief Set the ADC2ALTTRGEN field to a new value. */
#define BW_SIM_SOPT7_ADC2ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC2ALTTRGEN) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC3TRGSEL[27:24] (RW)
 *
 * Selects the ADC3 trigger source when alternative triggers are enabled through
 * ADC3ALTTRGEN.
 *
 * Values:
 * - 0000 - External trigger
 * - 0001 - High speed comparator 0 asynchronous interrupt
 * - 0010 - High speed comparator 1 asynchronous interrupt
 * - 0011 - High speed comparator 2 asynchronous interrupt
 * - 0100 - PIT trigger 0
 * - 0101 - PIT trigger 1
 * - 0110 - PIT trigger 2
 * - 0111 - PIT trigger 3
 * - 1000 - FTM0 trigger
 * - 1001 - FTM1 trigger
 * - 1010 - FTM2 trigger
 * - 1011 - FTM3 trigger
 * - 1100 - RTC alarm
 * - 1101 - RTC seconds
 * - 1110 - Low-power timer trigger
 * - 1111 - High speed comparator 3 asynchronous interrupt
 */
/*@{*/
#define BP_SIM_SOPT7_ADC3TRGSEL (24U)      /*!< Bit position for SIM_SOPT7_ADC3TRGSEL. */
#define BM_SIM_SOPT7_ADC3TRGSEL (0x0F000000U) /*!< Bit mask for SIM_SOPT7_ADC3TRGSEL. */
#define BS_SIM_SOPT7_ADC3TRGSEL (4U)       /*!< Bit field size in bits for SIM_SOPT7_ADC3TRGSEL. */

/*! @brief Read current value of the SIM_SOPT7_ADC3TRGSEL field. */
#define BR_SIM_SOPT7_ADC3TRGSEL(x) (HW_SIM_SOPT7(x).B.ADC3TRGSEL)

/*! @brief Format value for bitfield SIM_SOPT7_ADC3TRGSEL. */
#define BF_SIM_SOPT7_ADC3TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC3TRGSEL) & BM_SIM_SOPT7_ADC3TRGSEL)

/*! @brief Set the ADC3TRGSEL field to a new value. */
#define BW_SIM_SOPT7_ADC3TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC3TRGSEL) | BF_SIM_SOPT7_ADC3TRGSEL(v)))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC3PRETRGSEL[28] (RW)
 *
 * Selects the ADC3 pre-trigger source when alternative triggers are enabled
 * through ADC3ALTTRGEN.
 *
 * Values:
 * - 0 - Pre-trigger A selected for ADC3.
 * - 1 - Pre-trigger B selected for ADC3.
 */
/*@{*/
#define BP_SIM_SOPT7_ADC3PRETRGSEL (28U)   /*!< Bit position for SIM_SOPT7_ADC3PRETRGSEL. */
#define BM_SIM_SOPT7_ADC3PRETRGSEL (0x10000000U) /*!< Bit mask for SIM_SOPT7_ADC3PRETRGSEL. */
#define BS_SIM_SOPT7_ADC3PRETRGSEL (1U)    /*!< Bit field size in bits for SIM_SOPT7_ADC3PRETRGSEL. */

/*! @brief Read current value of the SIM_SOPT7_ADC3PRETRGSEL field. */
#define BR_SIM_SOPT7_ADC3PRETRGSEL(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC3PRETRGSEL))

/*! @brief Format value for bitfield SIM_SOPT7_ADC3PRETRGSEL. */
#define BF_SIM_SOPT7_ADC3PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC3PRETRGSEL) & BM_SIM_SOPT7_ADC3PRETRGSEL)

/*! @brief Set the ADC3PRETRGSEL field to a new value. */
#define BW_SIM_SOPT7_ADC3PRETRGSEL(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC3PRETRGSEL) = (v))
/*@}*/

/*!
 * @name Register SIM_SOPT7, field ADC3ALTTRGEN[31] (RW)
 *
 * Enable alternative conversion triggers for ADC3.
 *
 * Values:
 * - 0 - PDB trigger selected for ADC3.
 * - 1 - Alternate trigger selected for ADC3.
 */
/*@{*/
#define BP_SIM_SOPT7_ADC3ALTTRGEN (31U)    /*!< Bit position for SIM_SOPT7_ADC3ALTTRGEN. */
#define BM_SIM_SOPT7_ADC3ALTTRGEN (0x80000000U) /*!< Bit mask for SIM_SOPT7_ADC3ALTTRGEN. */
#define BS_SIM_SOPT7_ADC3ALTTRGEN (1U)     /*!< Bit field size in bits for SIM_SOPT7_ADC3ALTTRGEN. */

/*! @brief Read current value of the SIM_SOPT7_ADC3ALTTRGEN field. */
#define BR_SIM_SOPT7_ADC3ALTTRGEN(x) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC3ALTTRGEN))

/*! @brief Format value for bitfield SIM_SOPT7_ADC3ALTTRGEN. */
#define BF_SIM_SOPT7_ADC3ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC3ALTTRGEN) & BM_SIM_SOPT7_ADC3ALTTRGEN)

/*! @brief Set the ADC3ALTTRGEN field to a new value. */
#define BW_SIM_SOPT7_ADC3ALTTRGEN(x, v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC3ALTTRGEN) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SDID - System Device Identification Register
 ******************************************************************************/

/*!
 * @brief HW_SIM_SDID - System Device Identification Register (RO)
 *
 * Reset value: 0x00000180U
 */
typedef union _hw_sim_sdid
{
    uint32_t U;
    struct _hw_sim_sdid_bitfields
    {
        uint32_t PINID : 4;            /*!< [3:0] Pincount identification */
        uint32_t FAMID : 3;            /*!< [6:4] Kinetis family identification */
        uint32_t RESERVED0 : 5;        /*!< [11:7]  */
        uint32_t REVID : 4;            /*!< [15:12] Device revision number */
        uint32_t RESERVED1 : 16;       /*!< [31:16]  */
    } B;
} hw_sim_sdid_t;

/*!
 * @name Constants and macros for entire SIM_SDID register
 */
/*@{*/
#define HW_SIM_SDID_ADDR(x)      ((x) + 0x1024U)

#define HW_SIM_SDID(x)           (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR(x))
#define HW_SIM_SDID_RD(x)        (HW_SIM_SDID(x).U)
/*@}*/

/*
 * Constants & macros for individual SIM_SDID bitfields
 */

/*!
 * @name Register SIM_SDID, field PINID[3:0] (RO)
 *
 * Specifies the pincount of the device.
 *
 * Values:
 * - 0000 - Reserved
 * - 0001 - Reserved
 * - 0010 - Reserved
 * - 0011 - Reserved
 * - 0100 - Reserved
 * - 0101 - Reserved
 * - 0110 - Reserved
 * - 0111 - Reserved
 * - 1000 - Reserved
 * - 1001 - Reserved
 * - 1010 - 144-pin
 * - 1011 - Reserved
 * - 1100 - 196-pin
 * - 1101 - Reserved
 * - 1110 - 256-pin
 * - 1111 - Reserved
 */
/*@{*/
#define BP_SIM_SDID_PINID    (0U)          /*!< Bit position for SIM_SDID_PINID. */
#define BM_SIM_SDID_PINID    (0x0000000FU) /*!< Bit mask for SIM_SDID_PINID. */
#define BS_SIM_SDID_PINID    (4U)          /*!< Bit field size in bits for SIM_SDID_PINID. */

/*! @brief Read current value of the SIM_SDID_PINID field. */
#define BR_SIM_SDID_PINID(x) (HW_SIM_SDID(x).B.PINID)
/*@}*/

/*!
 * @name Register SIM_SDID, field FAMID[6:4] (RO)
 *
 * Specifies the Kinetis family of the device.
 *
 * Values:
 * - 000 - K10
 * - 001 - K20
 * - 010 - K61
 * - 011 - Reserved
 * - 100 - K60
 * - 101 - K70
 * - 110 - Reserved
 * - 111 - Reserved
 */
/*@{*/
#define BP_SIM_SDID_FAMID    (4U)          /*!< Bit position for SIM_SDID_FAMID. */
#define BM_SIM_SDID_FAMID    (0x00000070U) /*!< Bit mask for SIM_SDID_FAMID. */
#define BS_SIM_SDID_FAMID    (3U)          /*!< Bit field size in bits for SIM_SDID_FAMID. */

/*! @brief Read current value of the SIM_SDID_FAMID field. */
#define BR_SIM_SDID_FAMID(x) (HW_SIM_SDID(x).B.FAMID)
/*@}*/

/*!
 * @name Register SIM_SDID, field REVID[15:12] (RO)
 *
 * Specifies the silicon implementation number for the device.
 */
/*@{*/
#define BP_SIM_SDID_REVID    (12U)         /*!< Bit position for SIM_SDID_REVID. */
#define BM_SIM_SDID_REVID    (0x0000F000U) /*!< Bit mask for SIM_SDID_REVID. */
#define BS_SIM_SDID_REVID    (4U)          /*!< Bit field size in bits for SIM_SDID_REVID. */

/*! @brief Read current value of the SIM_SDID_REVID field. */
#define BR_SIM_SDID_REVID(x) (HW_SIM_SDID(x).B.REVID)
/*@}*/

/*******************************************************************************
 * HW_SIM_SCGC1 - System Clock Gating Control Register 1
 ******************************************************************************/

/*!
 * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_scgc1
{
    uint32_t U;
    struct _hw_sim_scgc1_bitfields
    {
        uint32_t RESERVED0 : 5;        /*!< [4:0]  */
        uint32_t OSC1b : 1;            /*!< [5] OSC1 clock gate control */
        uint32_t RESERVED1 : 4;        /*!< [9:6]  */
        uint32_t UART4b : 1;           /*!< [10] UART4 clock gate control */
        uint32_t UART5b : 1;           /*!< [11] UART5 clock gate control */
        uint32_t RESERVED2 : 20;       /*!< [31:12]  */
    } B;
} hw_sim_scgc1_t;

/*!
 * @name Constants and macros for entire SIM_SCGC1 register
 */
/*@{*/
#define HW_SIM_SCGC1_ADDR(x)     ((x) + 0x1028U)

#define HW_SIM_SCGC1(x)          (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR(x))
#define HW_SIM_SCGC1_RD(x)       (HW_SIM_SCGC1(x).U)
#define HW_SIM_SCGC1_WR(x, v)    (HW_SIM_SCGC1(x).U = (v))
#define HW_SIM_SCGC1_SET(x, v)   (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) |  (v)))
#define HW_SIM_SCGC1_CLR(x, v)   (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) & ~(v)))
#define HW_SIM_SCGC1_TOG(x, v)   (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SCGC1 bitfields
 */

/*!
 * @name Register SIM_SCGC1, field OSC1[5] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC1_OSC1    (5U)          /*!< Bit position for SIM_SCGC1_OSC1. */
#define BM_SIM_SCGC1_OSC1    (0x00000020U) /*!< Bit mask for SIM_SCGC1_OSC1. */
#define BS_SIM_SCGC1_OSC1    (1U)          /*!< Bit field size in bits for SIM_SCGC1_OSC1. */

/*! @brief Read current value of the SIM_SCGC1_OSC1 field. */
#define BR_SIM_SCGC1_OSC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_OSC1))

/*! @brief Format value for bitfield SIM_SCGC1_OSC1. */
#define BF_SIM_SCGC1_OSC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_OSC1) & BM_SIM_SCGC1_OSC1)

/*! @brief Set the OSC1 field to a new value. */
#define BW_SIM_SCGC1_OSC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_OSC1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC1, field UART4[10] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC1_UART4   (10U)         /*!< Bit position for SIM_SCGC1_UART4. */
#define BM_SIM_SCGC1_UART4   (0x00000400U) /*!< Bit mask for SIM_SCGC1_UART4. */
#define BS_SIM_SCGC1_UART4   (1U)          /*!< Bit field size in bits for SIM_SCGC1_UART4. */

/*! @brief Read current value of the SIM_SCGC1_UART4 field. */
#define BR_SIM_SCGC1_UART4(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4))

/*! @brief Format value for bitfield SIM_SCGC1_UART4. */
#define BF_SIM_SCGC1_UART4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART4) & BM_SIM_SCGC1_UART4)

/*! @brief Set the UART4 field to a new value. */
#define BW_SIM_SCGC1_UART4(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC1, field UART5[11] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC1_UART5   (11U)         /*!< Bit position for SIM_SCGC1_UART5. */
#define BM_SIM_SCGC1_UART5   (0x00000800U) /*!< Bit mask for SIM_SCGC1_UART5. */
#define BS_SIM_SCGC1_UART5   (1U)          /*!< Bit field size in bits for SIM_SCGC1_UART5. */

/*! @brief Read current value of the SIM_SCGC1_UART5 field. */
#define BR_SIM_SCGC1_UART5(x) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5))

/*! @brief Format value for bitfield SIM_SCGC1_UART5. */
#define BF_SIM_SCGC1_UART5(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART5) & BM_SIM_SCGC1_UART5)

/*! @brief Set the UART5 field to a new value. */
#define BW_SIM_SCGC1_UART5(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SCGC2 - System Clock Gating Control Register 2
 ******************************************************************************/

/*!
 * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_scgc2
{
    uint32_t U;
    struct _hw_sim_scgc2_bitfields
    {
        uint32_t ENETb : 1;            /*!< [0] ENET clock gate control */
        uint32_t RESERVED0 : 11;       /*!< [11:1]  */
        uint32_t DAC0b : 1;            /*!< [12] 12BDAC0 clock gate control */
        uint32_t DAC1b : 1;            /*!< [13] 12BDAC1 clock gate control */
        uint32_t RESERVED1 : 18;       /*!< [31:14]  */
    } B;
} hw_sim_scgc2_t;

/*!
 * @name Constants and macros for entire SIM_SCGC2 register
 */
/*@{*/
#define HW_SIM_SCGC2_ADDR(x)     ((x) + 0x102CU)

#define HW_SIM_SCGC2(x)          (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR(x))
#define HW_SIM_SCGC2_RD(x)       (HW_SIM_SCGC2(x).U)
#define HW_SIM_SCGC2_WR(x, v)    (HW_SIM_SCGC2(x).U = (v))
#define HW_SIM_SCGC2_SET(x, v)   (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) |  (v)))
#define HW_SIM_SCGC2_CLR(x, v)   (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) & ~(v)))
#define HW_SIM_SCGC2_TOG(x, v)   (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SCGC2 bitfields
 */

/*!
 * @name Register SIM_SCGC2, field ENET[0] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC2_ENET    (0U)          /*!< Bit position for SIM_SCGC2_ENET. */
#define BM_SIM_SCGC2_ENET    (0x00000001U) /*!< Bit mask for SIM_SCGC2_ENET. */
#define BS_SIM_SCGC2_ENET    (1U)          /*!< Bit field size in bits for SIM_SCGC2_ENET. */

/*! @brief Read current value of the SIM_SCGC2_ENET field. */
#define BR_SIM_SCGC2_ENET(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET))

/*! @brief Format value for bitfield SIM_SCGC2_ENET. */
#define BF_SIM_SCGC2_ENET(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_ENET) & BM_SIM_SCGC2_ENET)

/*! @brief Set the ENET field to a new value. */
#define BW_SIM_SCGC2_ENET(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC2, field DAC0[12] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC2_DAC0    (12U)         /*!< Bit position for SIM_SCGC2_DAC0. */
#define BM_SIM_SCGC2_DAC0    (0x00001000U) /*!< Bit mask for SIM_SCGC2_DAC0. */
#define BS_SIM_SCGC2_DAC0    (1U)          /*!< Bit field size in bits for SIM_SCGC2_DAC0. */

/*! @brief Read current value of the SIM_SCGC2_DAC0 field. */
#define BR_SIM_SCGC2_DAC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0))

/*! @brief Format value for bitfield SIM_SCGC2_DAC0. */
#define BF_SIM_SCGC2_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC0) & BM_SIM_SCGC2_DAC0)

/*! @brief Set the DAC0 field to a new value. */
#define BW_SIM_SCGC2_DAC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC2, field DAC1[13] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC2_DAC1    (13U)         /*!< Bit position for SIM_SCGC2_DAC1. */
#define BM_SIM_SCGC2_DAC1    (0x00002000U) /*!< Bit mask for SIM_SCGC2_DAC1. */
#define BS_SIM_SCGC2_DAC1    (1U)          /*!< Bit field size in bits for SIM_SCGC2_DAC1. */

/*! @brief Read current value of the SIM_SCGC2_DAC1 field. */
#define BR_SIM_SCGC2_DAC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1))

/*! @brief Format value for bitfield SIM_SCGC2_DAC1. */
#define BF_SIM_SCGC2_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC1) & BM_SIM_SCGC2_DAC1)

/*! @brief Set the DAC1 field to a new value. */
#define BW_SIM_SCGC2_DAC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SCGC3 - System Clock Gating Control Register 3
 ******************************************************************************/

/*!
 * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_scgc3
{
    uint32_t U;
    struct _hw_sim_scgc3_bitfields
    {
        uint32_t RNGA : 1;             /*!< [0] RNGA clock gate control */
        uint32_t RESERVED0 : 3;        /*!< [3:1]  */
        uint32_t FLEXCAN1 : 1;         /*!< [4] FlexCAN1 clock gate control */
        uint32_t RESERVED1 : 3;        /*!< [7:5]  */
        uint32_t NFCb : 1;             /*!< [8] NFC clock gate control */
        uint32_t RESERVED2 : 3;        /*!< [11:9]  */
        uint32_t DSPI2 : 1;            /*!< [12] DSPI2 clock gate control */
        uint32_t RESERVED3 : 2;        /*!< [14:13]  */
        uint32_t SAI1 : 1;             /*!< [15] SAI1 clock gate control */
        uint32_t RESERVED4 : 1;        /*!< [16]  */
        uint32_t ESDHC : 1;            /*!< [17] ESDHC clock gate control */
        uint32_t RESERVED5 : 4;        /*!< [21:18]  */
        uint32_t LCDCb : 1;            /*!< [22] LCDC clock gate control */
        uint32_t RESERVED6 : 1;        /*!< [23]  */
        uint32_t FTM2b : 1;            /*!< [24] FTM2 clock gate control */
        uint32_t FTM3b : 1;            /*!< [25] FTM3 clock gate control */
        uint32_t RESERVED7 : 1;        /*!< [26]  */
        uint32_t ADC1b : 1;            /*!< [27] ADC1 clock gate control */
        uint32_t ADC3b : 1;            /*!< [28] ADC3 clock gate control */
        uint32_t RESERVED8 : 3;        /*!< [31:29]  */
    } B;
} hw_sim_scgc3_t;

/*!
 * @name Constants and macros for entire SIM_SCGC3 register
 */
/*@{*/
#define HW_SIM_SCGC3_ADDR(x)     ((x) + 0x1030U)

#define HW_SIM_SCGC3(x)          (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR(x))
#define HW_SIM_SCGC3_RD(x)       (HW_SIM_SCGC3(x).U)
#define HW_SIM_SCGC3_WR(x, v)    (HW_SIM_SCGC3(x).U = (v))
#define HW_SIM_SCGC3_SET(x, v)   (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) |  (v)))
#define HW_SIM_SCGC3_CLR(x, v)   (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) & ~(v)))
#define HW_SIM_SCGC3_TOG(x, v)   (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SCGC3 bitfields
 */

/*!
 * @name Register SIM_SCGC3, field RNGA[0] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_RNGA    (0U)          /*!< Bit position for SIM_SCGC3_RNGA. */
#define BM_SIM_SCGC3_RNGA    (0x00000001U) /*!< Bit mask for SIM_SCGC3_RNGA. */
#define BS_SIM_SCGC3_RNGA    (1U)          /*!< Bit field size in bits for SIM_SCGC3_RNGA. */

/*! @brief Read current value of the SIM_SCGC3_RNGA field. */
#define BR_SIM_SCGC3_RNGA(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA))

/*! @brief Format value for bitfield SIM_SCGC3_RNGA. */
#define BF_SIM_SCGC3_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_RNGA) & BM_SIM_SCGC3_RNGA)

/*! @brief Set the RNGA field to a new value. */
#define BW_SIM_SCGC3_RNGA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field FLEXCAN1[4] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_FLEXCAN1 (4U)         /*!< Bit position for SIM_SCGC3_FLEXCAN1. */
#define BM_SIM_SCGC3_FLEXCAN1 (0x00000010U) /*!< Bit mask for SIM_SCGC3_FLEXCAN1. */
#define BS_SIM_SCGC3_FLEXCAN1 (1U)         /*!< Bit field size in bits for SIM_SCGC3_FLEXCAN1. */

/*! @brief Read current value of the SIM_SCGC3_FLEXCAN1 field. */
#define BR_SIM_SCGC3_FLEXCAN1(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FLEXCAN1))

/*! @brief Format value for bitfield SIM_SCGC3_FLEXCAN1. */
#define BF_SIM_SCGC3_FLEXCAN1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FLEXCAN1) & BM_SIM_SCGC3_FLEXCAN1)

/*! @brief Set the FLEXCAN1 field to a new value. */
#define BW_SIM_SCGC3_FLEXCAN1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FLEXCAN1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field NFC[8] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_NFC     (8U)          /*!< Bit position for SIM_SCGC3_NFC. */
#define BM_SIM_SCGC3_NFC     (0x00000100U) /*!< Bit mask for SIM_SCGC3_NFC. */
#define BS_SIM_SCGC3_NFC     (1U)          /*!< Bit field size in bits for SIM_SCGC3_NFC. */

/*! @brief Read current value of the SIM_SCGC3_NFC field. */
#define BR_SIM_SCGC3_NFC(x)  (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_NFC))

/*! @brief Format value for bitfield SIM_SCGC3_NFC. */
#define BF_SIM_SCGC3_NFC(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_NFC) & BM_SIM_SCGC3_NFC)

/*! @brief Set the NFC field to a new value. */
#define BW_SIM_SCGC3_NFC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_NFC) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field DSPI2[12] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_DSPI2   (12U)         /*!< Bit position for SIM_SCGC3_DSPI2. */
#define BM_SIM_SCGC3_DSPI2   (0x00001000U) /*!< Bit mask for SIM_SCGC3_DSPI2. */
#define BS_SIM_SCGC3_DSPI2   (1U)          /*!< Bit field size in bits for SIM_SCGC3_DSPI2. */

/*! @brief Read current value of the SIM_SCGC3_DSPI2 field. */
#define BR_SIM_SCGC3_DSPI2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_DSPI2))

/*! @brief Format value for bitfield SIM_SCGC3_DSPI2. */
#define BF_SIM_SCGC3_DSPI2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_DSPI2) & BM_SIM_SCGC3_DSPI2)

/*! @brief Set the DSPI2 field to a new value. */
#define BW_SIM_SCGC3_DSPI2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_DSPI2) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field SAI1[15] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_SAI1    (15U)         /*!< Bit position for SIM_SCGC3_SAI1. */
#define BM_SIM_SCGC3_SAI1    (0x00008000U) /*!< Bit mask for SIM_SCGC3_SAI1. */
#define BS_SIM_SCGC3_SAI1    (1U)          /*!< Bit field size in bits for SIM_SCGC3_SAI1. */

/*! @brief Read current value of the SIM_SCGC3_SAI1 field. */
#define BR_SIM_SCGC3_SAI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SAI1))

/*! @brief Format value for bitfield SIM_SCGC3_SAI1. */
#define BF_SIM_SCGC3_SAI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SAI1) & BM_SIM_SCGC3_SAI1)

/*! @brief Set the SAI1 field to a new value. */
#define BW_SIM_SCGC3_SAI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SAI1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field ESDHC[17] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_ESDHC   (17U)         /*!< Bit position for SIM_SCGC3_ESDHC. */
#define BM_SIM_SCGC3_ESDHC   (0x00020000U) /*!< Bit mask for SIM_SCGC3_ESDHC. */
#define BS_SIM_SCGC3_ESDHC   (1U)          /*!< Bit field size in bits for SIM_SCGC3_ESDHC. */

/*! @brief Read current value of the SIM_SCGC3_ESDHC field. */
#define BR_SIM_SCGC3_ESDHC(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ESDHC))

/*! @brief Format value for bitfield SIM_SCGC3_ESDHC. */
#define BF_SIM_SCGC3_ESDHC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ESDHC) & BM_SIM_SCGC3_ESDHC)

/*! @brief Set the ESDHC field to a new value. */
#define BW_SIM_SCGC3_ESDHC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ESDHC) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field LCDC[22] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_LCDC    (22U)         /*!< Bit position for SIM_SCGC3_LCDC. */
#define BM_SIM_SCGC3_LCDC    (0x00400000U) /*!< Bit mask for SIM_SCGC3_LCDC. */
#define BS_SIM_SCGC3_LCDC    (1U)          /*!< Bit field size in bits for SIM_SCGC3_LCDC. */

/*! @brief Read current value of the SIM_SCGC3_LCDC field. */
#define BR_SIM_SCGC3_LCDC(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_LCDC))

/*! @brief Format value for bitfield SIM_SCGC3_LCDC. */
#define BF_SIM_SCGC3_LCDC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_LCDC) & BM_SIM_SCGC3_LCDC)

/*! @brief Set the LCDC field to a new value. */
#define BW_SIM_SCGC3_LCDC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_LCDC) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field FTM2[24] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_FTM2    (24U)         /*!< Bit position for SIM_SCGC3_FTM2. */
#define BM_SIM_SCGC3_FTM2    (0x01000000U) /*!< Bit mask for SIM_SCGC3_FTM2. */
#define BS_SIM_SCGC3_FTM2    (1U)          /*!< Bit field size in bits for SIM_SCGC3_FTM2. */

/*! @brief Read current value of the SIM_SCGC3_FTM2 field. */
#define BR_SIM_SCGC3_FTM2(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2))

/*! @brief Format value for bitfield SIM_SCGC3_FTM2. */
#define BF_SIM_SCGC3_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM2) & BM_SIM_SCGC3_FTM2)

/*! @brief Set the FTM2 field to a new value. */
#define BW_SIM_SCGC3_FTM2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field FTM3[25] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_FTM3    (25U)         /*!< Bit position for SIM_SCGC3_FTM3. */
#define BM_SIM_SCGC3_FTM3    (0x02000000U) /*!< Bit mask for SIM_SCGC3_FTM3. */
#define BS_SIM_SCGC3_FTM3    (1U)          /*!< Bit field size in bits for SIM_SCGC3_FTM3. */

/*! @brief Read current value of the SIM_SCGC3_FTM3 field. */
#define BR_SIM_SCGC3_FTM3(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3))

/*! @brief Format value for bitfield SIM_SCGC3_FTM3. */
#define BF_SIM_SCGC3_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM3) & BM_SIM_SCGC3_FTM3)

/*! @brief Set the FTM3 field to a new value. */
#define BW_SIM_SCGC3_FTM3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field ADC1[27] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_ADC1    (27U)         /*!< Bit position for SIM_SCGC3_ADC1. */
#define BM_SIM_SCGC3_ADC1    (0x08000000U) /*!< Bit mask for SIM_SCGC3_ADC1. */
#define BS_SIM_SCGC3_ADC1    (1U)          /*!< Bit field size in bits for SIM_SCGC3_ADC1. */

/*! @brief Read current value of the SIM_SCGC3_ADC1 field. */
#define BR_SIM_SCGC3_ADC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1))

/*! @brief Format value for bitfield SIM_SCGC3_ADC1. */
#define BF_SIM_SCGC3_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ADC1) & BM_SIM_SCGC3_ADC1)

/*! @brief Set the ADC1 field to a new value. */
#define BW_SIM_SCGC3_ADC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC3, field ADC3[28] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC3_ADC3    (28U)         /*!< Bit position for SIM_SCGC3_ADC3. */
#define BM_SIM_SCGC3_ADC3    (0x10000000U) /*!< Bit mask for SIM_SCGC3_ADC3. */
#define BS_SIM_SCGC3_ADC3    (1U)          /*!< Bit field size in bits for SIM_SCGC3_ADC3. */

/*! @brief Read current value of the SIM_SCGC3_ADC3 field. */
#define BR_SIM_SCGC3_ADC3(x) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC3))

/*! @brief Format value for bitfield SIM_SCGC3_ADC3. */
#define BF_SIM_SCGC3_ADC3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ADC3) & BM_SIM_SCGC3_ADC3)

/*! @brief Set the ADC3 field to a new value. */
#define BW_SIM_SCGC3_ADC3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC3) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SCGC4 - System Clock Gating Control Register 4
 ******************************************************************************/

/*!
 * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
 *
 * Reset value: 0xF0100030U
 */
typedef union _hw_sim_scgc4
{
    uint32_t U;
    struct _hw_sim_scgc4_bitfields
    {
        uint32_t RESERVED0 : 1;        /*!< [0]  */
        uint32_t EWMb : 1;             /*!< [1] EWM clock gate control */
        uint32_t CMTb : 1;             /*!< [2] CMT clock gate control */
        uint32_t RESERVED1 : 3;        /*!< [5:3]  */
        uint32_t IIC0 : 1;             /*!< [6] IIC0 clock gate control */
        uint32_t IIC1 : 1;             /*!< [7] IIC1 clock gate control */
        uint32_t RESERVED2 : 2;        /*!< [9:8]  */
        uint32_t UART0b : 1;           /*!< [10] UART0 clock gate control */
        uint32_t UART1b : 1;           /*!< [11] UART1 clock gate control */
        uint32_t UART2b : 1;           /*!< [12] UART2 clock gate control */
        uint32_t UART3b : 1;           /*!< [13] UART3 clock gate control */
        uint32_t RESERVED3 : 4;        /*!< [17:14]  */
        uint32_t USBFS : 1;            /*!< [18] USB FS clock gate control */
        uint32_t CMP : 1;              /*!< [19] Comparator clock gate control */
        uint32_t VREFb : 1;            /*!< [20] VREF clock gate control */
        uint32_t RESERVED4 : 7;        /*!< [27:21]  */
        uint32_t LLWUb : 1;            /*!< [28] LLWU Clock Gate Control */
        uint32_t RESERVED5 : 3;        /*!< [31:29]  */
    } B;
} hw_sim_scgc4_t;

/*!
 * @name Constants and macros for entire SIM_SCGC4 register
 */
/*@{*/
#define HW_SIM_SCGC4_ADDR(x)     ((x) + 0x1034U)

#define HW_SIM_SCGC4(x)          (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR(x))
#define HW_SIM_SCGC4_RD(x)       (HW_SIM_SCGC4(x).U)
#define HW_SIM_SCGC4_WR(x, v)    (HW_SIM_SCGC4(x).U = (v))
#define HW_SIM_SCGC4_SET(x, v)   (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) |  (v)))
#define HW_SIM_SCGC4_CLR(x, v)   (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v)))
#define HW_SIM_SCGC4_TOG(x, v)   (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SCGC4 bitfields
 */

/*!
 * @name Register SIM_SCGC4, field EWM[1] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_EWM     (1U)          /*!< Bit position for SIM_SCGC4_EWM. */
#define BM_SIM_SCGC4_EWM     (0x00000002U) /*!< Bit mask for SIM_SCGC4_EWM. */
#define BS_SIM_SCGC4_EWM     (1U)          /*!< Bit field size in bits for SIM_SCGC4_EWM. */

/*! @brief Read current value of the SIM_SCGC4_EWM field. */
#define BR_SIM_SCGC4_EWM(x)  (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM))

/*! @brief Format value for bitfield SIM_SCGC4_EWM. */
#define BF_SIM_SCGC4_EWM(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM)

/*! @brief Set the EWM field to a new value. */
#define BW_SIM_SCGC4_EWM(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field CMT[2] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_CMT     (2U)          /*!< Bit position for SIM_SCGC4_CMT. */
#define BM_SIM_SCGC4_CMT     (0x00000004U) /*!< Bit mask for SIM_SCGC4_CMT. */
#define BS_SIM_SCGC4_CMT     (1U)          /*!< Bit field size in bits for SIM_SCGC4_CMT. */

/*! @brief Read current value of the SIM_SCGC4_CMT field. */
#define BR_SIM_SCGC4_CMT(x)  (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT))

/*! @brief Format value for bitfield SIM_SCGC4_CMT. */
#define BF_SIM_SCGC4_CMT(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMT) & BM_SIM_SCGC4_CMT)

/*! @brief Set the CMT field to a new value. */
#define BW_SIM_SCGC4_CMT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field IIC0[6] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_IIC0    (6U)          /*!< Bit position for SIM_SCGC4_IIC0. */
#define BM_SIM_SCGC4_IIC0    (0x00000040U) /*!< Bit mask for SIM_SCGC4_IIC0. */
#define BS_SIM_SCGC4_IIC0    (1U)          /*!< Bit field size in bits for SIM_SCGC4_IIC0. */

/*! @brief Read current value of the SIM_SCGC4_IIC0 field. */
#define BR_SIM_SCGC4_IIC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_IIC0))

/*! @brief Format value for bitfield SIM_SCGC4_IIC0. */
#define BF_SIM_SCGC4_IIC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_IIC0) & BM_SIM_SCGC4_IIC0)

/*! @brief Set the IIC0 field to a new value. */
#define BW_SIM_SCGC4_IIC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_IIC0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field IIC1[7] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_IIC1    (7U)          /*!< Bit position for SIM_SCGC4_IIC1. */
#define BM_SIM_SCGC4_IIC1    (0x00000080U) /*!< Bit mask for SIM_SCGC4_IIC1. */
#define BS_SIM_SCGC4_IIC1    (1U)          /*!< Bit field size in bits for SIM_SCGC4_IIC1. */

/*! @brief Read current value of the SIM_SCGC4_IIC1 field. */
#define BR_SIM_SCGC4_IIC1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_IIC1))

/*! @brief Format value for bitfield SIM_SCGC4_IIC1. */
#define BF_SIM_SCGC4_IIC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_IIC1) & BM_SIM_SCGC4_IIC1)

/*! @brief Set the IIC1 field to a new value. */
#define BW_SIM_SCGC4_IIC1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_IIC1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field UART0[10] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_UART0   (10U)         /*!< Bit position for SIM_SCGC4_UART0. */
#define BM_SIM_SCGC4_UART0   (0x00000400U) /*!< Bit mask for SIM_SCGC4_UART0. */
#define BS_SIM_SCGC4_UART0   (1U)          /*!< Bit field size in bits for SIM_SCGC4_UART0. */

/*! @brief Read current value of the SIM_SCGC4_UART0 field. */
#define BR_SIM_SCGC4_UART0(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0))

/*! @brief Format value for bitfield SIM_SCGC4_UART0. */
#define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0)

/*! @brief Set the UART0 field to a new value. */
#define BW_SIM_SCGC4_UART0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field UART1[11] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_UART1   (11U)         /*!< Bit position for SIM_SCGC4_UART1. */
#define BM_SIM_SCGC4_UART1   (0x00000800U) /*!< Bit mask for SIM_SCGC4_UART1. */
#define BS_SIM_SCGC4_UART1   (1U)          /*!< Bit field size in bits for SIM_SCGC4_UART1. */

/*! @brief Read current value of the SIM_SCGC4_UART1 field. */
#define BR_SIM_SCGC4_UART1(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1))

/*! @brief Format value for bitfield SIM_SCGC4_UART1. */
#define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1)

/*! @brief Set the UART1 field to a new value. */
#define BW_SIM_SCGC4_UART1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field UART2[12] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_UART2   (12U)         /*!< Bit position for SIM_SCGC4_UART2. */
#define BM_SIM_SCGC4_UART2   (0x00001000U) /*!< Bit mask for SIM_SCGC4_UART2. */
#define BS_SIM_SCGC4_UART2   (1U)          /*!< Bit field size in bits for SIM_SCGC4_UART2. */

/*! @brief Read current value of the SIM_SCGC4_UART2 field. */
#define BR_SIM_SCGC4_UART2(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2))

/*! @brief Format value for bitfield SIM_SCGC4_UART2. */
#define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2)

/*! @brief Set the UART2 field to a new value. */
#define BW_SIM_SCGC4_UART2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field UART3[13] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_UART3   (13U)         /*!< Bit position for SIM_SCGC4_UART3. */
#define BM_SIM_SCGC4_UART3   (0x00002000U) /*!< Bit mask for SIM_SCGC4_UART3. */
#define BS_SIM_SCGC4_UART3   (1U)          /*!< Bit field size in bits for SIM_SCGC4_UART3. */

/*! @brief Read current value of the SIM_SCGC4_UART3 field. */
#define BR_SIM_SCGC4_UART3(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3))

/*! @brief Format value for bitfield SIM_SCGC4_UART3. */
#define BF_SIM_SCGC4_UART3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART3) & BM_SIM_SCGC4_UART3)

/*! @brief Set the UART3 field to a new value. */
#define BW_SIM_SCGC4_UART3(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field USBFS[18] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_USBFS   (18U)         /*!< Bit position for SIM_SCGC4_USBFS. */
#define BM_SIM_SCGC4_USBFS   (0x00040000U) /*!< Bit mask for SIM_SCGC4_USBFS. */
#define BS_SIM_SCGC4_USBFS   (1U)          /*!< Bit field size in bits for SIM_SCGC4_USBFS. */

/*! @brief Read current value of the SIM_SCGC4_USBFS field. */
#define BR_SIM_SCGC4_USBFS(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBFS))

/*! @brief Format value for bitfield SIM_SCGC4_USBFS. */
#define BF_SIM_SCGC4_USBFS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBFS) & BM_SIM_SCGC4_USBFS)

/*! @brief Set the USBFS field to a new value. */
#define BW_SIM_SCGC4_USBFS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBFS) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field CMP[19] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_CMP     (19U)         /*!< Bit position for SIM_SCGC4_CMP. */
#define BM_SIM_SCGC4_CMP     (0x00080000U) /*!< Bit mask for SIM_SCGC4_CMP. */
#define BS_SIM_SCGC4_CMP     (1U)          /*!< Bit field size in bits for SIM_SCGC4_CMP. */

/*! @brief Read current value of the SIM_SCGC4_CMP field. */
#define BR_SIM_SCGC4_CMP(x)  (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP))

/*! @brief Format value for bitfield SIM_SCGC4_CMP. */
#define BF_SIM_SCGC4_CMP(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP)

/*! @brief Set the CMP field to a new value. */
#define BW_SIM_SCGC4_CMP(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field VREF[20] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_VREF    (20U)         /*!< Bit position for SIM_SCGC4_VREF. */
#define BM_SIM_SCGC4_VREF    (0x00100000U) /*!< Bit mask for SIM_SCGC4_VREF. */
#define BS_SIM_SCGC4_VREF    (1U)          /*!< Bit field size in bits for SIM_SCGC4_VREF. */

/*! @brief Read current value of the SIM_SCGC4_VREF field. */
#define BR_SIM_SCGC4_VREF(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF))

/*! @brief Format value for bitfield SIM_SCGC4_VREF. */
#define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF)

/*! @brief Set the VREF field to a new value. */
#define BW_SIM_SCGC4_VREF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC4, field LLWU[28] (RW)
 *
 * This bit controls the clock gate to the LLWU module.
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC4_LLWU    (28U)         /*!< Bit position for SIM_SCGC4_LLWU. */
#define BM_SIM_SCGC4_LLWU    (0x10000000U) /*!< Bit mask for SIM_SCGC4_LLWU. */
#define BS_SIM_SCGC4_LLWU    (1U)          /*!< Bit field size in bits for SIM_SCGC4_LLWU. */

/*! @brief Read current value of the SIM_SCGC4_LLWU field. */
#define BR_SIM_SCGC4_LLWU(x) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_LLWU))

/*! @brief Format value for bitfield SIM_SCGC4_LLWU. */
#define BF_SIM_SCGC4_LLWU(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_LLWU) & BM_SIM_SCGC4_LLWU)

/*! @brief Set the LLWU field to a new value. */
#define BW_SIM_SCGC4_LLWU(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_LLWU) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SCGC5 - System Clock Gating Control Register 5
 ******************************************************************************/

/*!
 * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
 *
 * Reset value: 0x00040180U
 */
typedef union _hw_sim_scgc5
{
    uint32_t U;
    struct _hw_sim_scgc5_bitfields
    {
        uint32_t LPTIMER : 1;          /*!< [0] LPTMR clock gate control */
        uint32_t REGFILE : 1;          /*!< [1] Register File Clock Gate Control */
        uint32_t DRYICE : 1;           /*!< [2] Dryice clock gate control */
        uint32_t DRYICESECREG : 1;     /*!< [3] Dryice secure storage clock gate
                                        * control */
        uint32_t RESERVED0 : 1;        /*!< [4]  */
        uint32_t TSI : 1;              /*!< [5] TSI clock gate control */
        uint32_t RESERVED1 : 3;        /*!< [8:6]  */
        uint32_t PORTAb : 1;           /*!< [9] PORTA clock gate control */
        uint32_t PORTBb : 1;           /*!< [10] PORTB clock gate control */
        uint32_t PORTCb : 1;           /*!< [11] PORTC clock gate control */
        uint32_t PORTDb : 1;           /*!< [12] PORTD clock gate control */
        uint32_t PORTEb : 1;           /*!< [13] PORTE clock gate control */
        uint32_t PORTFb : 1;           /*!< [14] PORTF clock gate control */
        uint32_t RESERVED2 : 17;       /*!< [31:15]  */
    } B;
} hw_sim_scgc5_t;

/*!
 * @name Constants and macros for entire SIM_SCGC5 register
 */
/*@{*/
#define HW_SIM_SCGC5_ADDR(x)     ((x) + 0x1038U)

#define HW_SIM_SCGC5(x)          (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR(x))
#define HW_SIM_SCGC5_RD(x)       (HW_SIM_SCGC5(x).U)
#define HW_SIM_SCGC5_WR(x, v)    (HW_SIM_SCGC5(x).U = (v))
#define HW_SIM_SCGC5_SET(x, v)   (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) |  (v)))
#define HW_SIM_SCGC5_CLR(x, v)   (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v)))
#define HW_SIM_SCGC5_TOG(x, v)   (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SCGC5 bitfields
 */

/*!
 * @name Register SIM_SCGC5, field LPTIMER[0] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_LPTIMER (0U)          /*!< Bit position for SIM_SCGC5_LPTIMER. */
#define BM_SIM_SCGC5_LPTIMER (0x00000001U) /*!< Bit mask for SIM_SCGC5_LPTIMER. */
#define BS_SIM_SCGC5_LPTIMER (1U)          /*!< Bit field size in bits for SIM_SCGC5_LPTIMER. */

/*! @brief Read current value of the SIM_SCGC5_LPTIMER field. */
#define BR_SIM_SCGC5_LPTIMER(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTIMER))

/*! @brief Format value for bitfield SIM_SCGC5_LPTIMER. */
#define BF_SIM_SCGC5_LPTIMER(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTIMER) & BM_SIM_SCGC5_LPTIMER)

/*! @brief Set the LPTIMER field to a new value. */
#define BW_SIM_SCGC5_LPTIMER(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTIMER) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field REGFILE[1] (RW)
 *
 * This bit controls the clock gate to the Register File module.
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_REGFILE (1U)          /*!< Bit position for SIM_SCGC5_REGFILE. */
#define BM_SIM_SCGC5_REGFILE (0x00000002U) /*!< Bit mask for SIM_SCGC5_REGFILE. */
#define BS_SIM_SCGC5_REGFILE (1U)          /*!< Bit field size in bits for SIM_SCGC5_REGFILE. */

/*! @brief Read current value of the SIM_SCGC5_REGFILE field. */
#define BR_SIM_SCGC5_REGFILE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_REGFILE))

/*! @brief Format value for bitfield SIM_SCGC5_REGFILE. */
#define BF_SIM_SCGC5_REGFILE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_REGFILE) & BM_SIM_SCGC5_REGFILE)

/*! @brief Set the REGFILE field to a new value. */
#define BW_SIM_SCGC5_REGFILE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_REGFILE) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field DRYICE[2] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_DRYICE  (2U)          /*!< Bit position for SIM_SCGC5_DRYICE. */
#define BM_SIM_SCGC5_DRYICE  (0x00000004U) /*!< Bit mask for SIM_SCGC5_DRYICE. */
#define BS_SIM_SCGC5_DRYICE  (1U)          /*!< Bit field size in bits for SIM_SCGC5_DRYICE. */

/*! @brief Read current value of the SIM_SCGC5_DRYICE field. */
#define BR_SIM_SCGC5_DRYICE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_DRYICE))

/*! @brief Format value for bitfield SIM_SCGC5_DRYICE. */
#define BF_SIM_SCGC5_DRYICE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_DRYICE) & BM_SIM_SCGC5_DRYICE)

/*! @brief Set the DRYICE field to a new value. */
#define BW_SIM_SCGC5_DRYICE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_DRYICE) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field DRYICESECREG[3] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_DRYICESECREG (3U)     /*!< Bit position for SIM_SCGC5_DRYICESECREG. */
#define BM_SIM_SCGC5_DRYICESECREG (0x00000008U) /*!< Bit mask for SIM_SCGC5_DRYICESECREG. */
#define BS_SIM_SCGC5_DRYICESECREG (1U)     /*!< Bit field size in bits for SIM_SCGC5_DRYICESECREG. */

/*! @brief Read current value of the SIM_SCGC5_DRYICESECREG field. */
#define BR_SIM_SCGC5_DRYICESECREG(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_DRYICESECREG))

/*! @brief Format value for bitfield SIM_SCGC5_DRYICESECREG. */
#define BF_SIM_SCGC5_DRYICESECREG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_DRYICESECREG) & BM_SIM_SCGC5_DRYICESECREG)

/*! @brief Set the DRYICESECREG field to a new value. */
#define BW_SIM_SCGC5_DRYICESECREG(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_DRYICESECREG) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field TSI[5] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_TSI     (5U)          /*!< Bit position for SIM_SCGC5_TSI. */
#define BM_SIM_SCGC5_TSI     (0x00000020U) /*!< Bit mask for SIM_SCGC5_TSI. */
#define BS_SIM_SCGC5_TSI     (1U)          /*!< Bit field size in bits for SIM_SCGC5_TSI. */

/*! @brief Read current value of the SIM_SCGC5_TSI field. */
#define BR_SIM_SCGC5_TSI(x)  (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_TSI))

/*! @brief Format value for bitfield SIM_SCGC5_TSI. */
#define BF_SIM_SCGC5_TSI(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_TSI) & BM_SIM_SCGC5_TSI)

/*! @brief Set the TSI field to a new value. */
#define BW_SIM_SCGC5_TSI(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_TSI) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field PORTA[9] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_PORTA   (9U)          /*!< Bit position for SIM_SCGC5_PORTA. */
#define BM_SIM_SCGC5_PORTA   (0x00000200U) /*!< Bit mask for SIM_SCGC5_PORTA. */
#define BS_SIM_SCGC5_PORTA   (1U)          /*!< Bit field size in bits for SIM_SCGC5_PORTA. */

/*! @brief Read current value of the SIM_SCGC5_PORTA field. */
#define BR_SIM_SCGC5_PORTA(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA))

/*! @brief Format value for bitfield SIM_SCGC5_PORTA. */
#define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA)

/*! @brief Set the PORTA field to a new value. */
#define BW_SIM_SCGC5_PORTA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field PORTB[10] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_PORTB   (10U)         /*!< Bit position for SIM_SCGC5_PORTB. */
#define BM_SIM_SCGC5_PORTB   (0x00000400U) /*!< Bit mask for SIM_SCGC5_PORTB. */
#define BS_SIM_SCGC5_PORTB   (1U)          /*!< Bit field size in bits for SIM_SCGC5_PORTB. */

/*! @brief Read current value of the SIM_SCGC5_PORTB field. */
#define BR_SIM_SCGC5_PORTB(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB))

/*! @brief Format value for bitfield SIM_SCGC5_PORTB. */
#define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB)

/*! @brief Set the PORTB field to a new value. */
#define BW_SIM_SCGC5_PORTB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field PORTC[11] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_PORTC   (11U)         /*!< Bit position for SIM_SCGC5_PORTC. */
#define BM_SIM_SCGC5_PORTC   (0x00000800U) /*!< Bit mask for SIM_SCGC5_PORTC. */
#define BS_SIM_SCGC5_PORTC   (1U)          /*!< Bit field size in bits for SIM_SCGC5_PORTC. */

/*! @brief Read current value of the SIM_SCGC5_PORTC field. */
#define BR_SIM_SCGC5_PORTC(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC))

/*! @brief Format value for bitfield SIM_SCGC5_PORTC. */
#define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC)

/*! @brief Set the PORTC field to a new value. */
#define BW_SIM_SCGC5_PORTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field PORTD[12] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_PORTD   (12U)         /*!< Bit position for SIM_SCGC5_PORTD. */
#define BM_SIM_SCGC5_PORTD   (0x00001000U) /*!< Bit mask for SIM_SCGC5_PORTD. */
#define BS_SIM_SCGC5_PORTD   (1U)          /*!< Bit field size in bits for SIM_SCGC5_PORTD. */

/*! @brief Read current value of the SIM_SCGC5_PORTD field. */
#define BR_SIM_SCGC5_PORTD(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD))

/*! @brief Format value for bitfield SIM_SCGC5_PORTD. */
#define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD)

/*! @brief Set the PORTD field to a new value. */
#define BW_SIM_SCGC5_PORTD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field PORTE[13] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_PORTE   (13U)         /*!< Bit position for SIM_SCGC5_PORTE. */
#define BM_SIM_SCGC5_PORTE   (0x00002000U) /*!< Bit mask for SIM_SCGC5_PORTE. */
#define BS_SIM_SCGC5_PORTE   (1U)          /*!< Bit field size in bits for SIM_SCGC5_PORTE. */

/*! @brief Read current value of the SIM_SCGC5_PORTE field. */
#define BR_SIM_SCGC5_PORTE(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE))

/*! @brief Format value for bitfield SIM_SCGC5_PORTE. */
#define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE)

/*! @brief Set the PORTE field to a new value. */
#define BW_SIM_SCGC5_PORTE(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC5, field PORTF[14] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC5_PORTF   (14U)         /*!< Bit position for SIM_SCGC5_PORTF. */
#define BM_SIM_SCGC5_PORTF   (0x00004000U) /*!< Bit mask for SIM_SCGC5_PORTF. */
#define BS_SIM_SCGC5_PORTF   (1U)          /*!< Bit field size in bits for SIM_SCGC5_PORTF. */

/*! @brief Read current value of the SIM_SCGC5_PORTF field. */
#define BR_SIM_SCGC5_PORTF(x) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTF))

/*! @brief Format value for bitfield SIM_SCGC5_PORTF. */
#define BF_SIM_SCGC5_PORTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTF) & BM_SIM_SCGC5_PORTF)

/*! @brief Set the PORTF field to a new value. */
#define BW_SIM_SCGC5_PORTF(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTF) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SCGC6 - System Clock Gating Control Register 6
 ******************************************************************************/

/*!
 * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
 *
 * Reset value: 0x40000001U
 */
typedef union _hw_sim_scgc6
{
    uint32_t U;
    struct _hw_sim_scgc6_bitfields
    {
        uint32_t RESERVED0 : 1;        /*!< [0]  */
        uint32_t DMAMUX0b : 1;         /*!< [1] DMAMUX0 clock gate control */
        uint32_t DMAMUX1b : 1;         /*!< [2] DMAMUX1 clock gate control */
        uint32_t RESERVED1 : 1;        /*!< [3]  */
        uint32_t FLEXCAN0 : 1;         /*!< [4] FlexCAN0 clock gate control */
        uint32_t RESERVED2 : 7;        /*!< [11:5]  */
        uint32_t DSPI0 : 1;            /*!< [12] DSPI0 clock gate control */
        uint32_t DSPI1 : 1;            /*!< [13] DSPI1 clock gate control */
        uint32_t RESERVED3 : 1;        /*!< [14]  */
        uint32_t SAI0 : 1;             /*!< [15] SAI0 clock gate control */
        uint32_t RESERVED4 : 2;        /*!< [17:16]  */
        uint32_t CRC : 1;              /*!< [18] CRC clock gate control */
        uint32_t RESERVED5 : 1;        /*!< [19]  */
        uint32_t USBHSb : 1;           /*!< [20] USBHS clock gate control */
        uint32_t USBDCDb : 1;          /*!< [21] USB DCD clock gate control */
        uint32_t PDB : 1;              /*!< [22] PDB clock gate control */
        uint32_t PITb : 1;             /*!< [23] PIT clock gate control */
        uint32_t FTM0b : 1;            /*!< [24] FTM0 clock gate control */
        uint32_t FTM1b : 1;            /*!< [25] FTM1 clock gate control */
        uint32_t RESERVED6 : 1;        /*!< [26]  */
        uint32_t ADC0b : 1;            /*!< [27] ADC0 clock gate control */
        uint32_t ADC2b : 1;            /*!< [28] ADC2 clock gate control */
        uint32_t RTCb : 1;             /*!< [29] RTC clock gate control */
        uint32_t RESERVED7 : 2;        /*!< [31:30]  */
    } B;
} hw_sim_scgc6_t;

/*!
 * @name Constants and macros for entire SIM_SCGC6 register
 */
/*@{*/
#define HW_SIM_SCGC6_ADDR(x)     ((x) + 0x103CU)

#define HW_SIM_SCGC6(x)          (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR(x))
#define HW_SIM_SCGC6_RD(x)       (HW_SIM_SCGC6(x).U)
#define HW_SIM_SCGC6_WR(x, v)    (HW_SIM_SCGC6(x).U = (v))
#define HW_SIM_SCGC6_SET(x, v)   (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) |  (v)))
#define HW_SIM_SCGC6_CLR(x, v)   (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v)))
#define HW_SIM_SCGC6_TOG(x, v)   (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SCGC6 bitfields
 */

/*!
 * @name Register SIM_SCGC6, field DMAMUX0[1] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_DMAMUX0 (1U)          /*!< Bit position for SIM_SCGC6_DMAMUX0. */
#define BM_SIM_SCGC6_DMAMUX0 (0x00000002U) /*!< Bit mask for SIM_SCGC6_DMAMUX0. */
#define BS_SIM_SCGC6_DMAMUX0 (1U)          /*!< Bit field size in bits for SIM_SCGC6_DMAMUX0. */

/*! @brief Read current value of the SIM_SCGC6_DMAMUX0 field. */
#define BR_SIM_SCGC6_DMAMUX0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX0))

/*! @brief Format value for bitfield SIM_SCGC6_DMAMUX0. */
#define BF_SIM_SCGC6_DMAMUX0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX0) & BM_SIM_SCGC6_DMAMUX0)

/*! @brief Set the DMAMUX0 field to a new value. */
#define BW_SIM_SCGC6_DMAMUX0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field DMAMUX1[2] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_DMAMUX1 (2U)          /*!< Bit position for SIM_SCGC6_DMAMUX1. */
#define BM_SIM_SCGC6_DMAMUX1 (0x00000004U) /*!< Bit mask for SIM_SCGC6_DMAMUX1. */
#define BS_SIM_SCGC6_DMAMUX1 (1U)          /*!< Bit field size in bits for SIM_SCGC6_DMAMUX1. */

/*! @brief Read current value of the SIM_SCGC6_DMAMUX1 field. */
#define BR_SIM_SCGC6_DMAMUX1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX1))

/*! @brief Format value for bitfield SIM_SCGC6_DMAMUX1. */
#define BF_SIM_SCGC6_DMAMUX1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX1) & BM_SIM_SCGC6_DMAMUX1)

/*! @brief Set the DMAMUX1 field to a new value. */
#define BW_SIM_SCGC6_DMAMUX1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_FLEXCAN0 (4U)         /*!< Bit position for SIM_SCGC6_FLEXCAN0. */
#define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) /*!< Bit mask for SIM_SCGC6_FLEXCAN0. */
#define BS_SIM_SCGC6_FLEXCAN0 (1U)         /*!< Bit field size in bits for SIM_SCGC6_FLEXCAN0. */

/*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */
#define BR_SIM_SCGC6_FLEXCAN0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0))

/*! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0. */
#define BF_SIM_SCGC6_FLEXCAN0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FLEXCAN0) & BM_SIM_SCGC6_FLEXCAN0)

/*! @brief Set the FLEXCAN0 field to a new value. */
#define BW_SIM_SCGC6_FLEXCAN0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field DSPI0[12] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_DSPI0   (12U)         /*!< Bit position for SIM_SCGC6_DSPI0. */
#define BM_SIM_SCGC6_DSPI0   (0x00001000U) /*!< Bit mask for SIM_SCGC6_DSPI0. */
#define BS_SIM_SCGC6_DSPI0   (1U)          /*!< Bit field size in bits for SIM_SCGC6_DSPI0. */

/*! @brief Read current value of the SIM_SCGC6_DSPI0 field. */
#define BR_SIM_SCGC6_DSPI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DSPI0))

/*! @brief Format value for bitfield SIM_SCGC6_DSPI0. */
#define BF_SIM_SCGC6_DSPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DSPI0) & BM_SIM_SCGC6_DSPI0)

/*! @brief Set the DSPI0 field to a new value. */
#define BW_SIM_SCGC6_DSPI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DSPI0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field DSPI1[13] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_DSPI1   (13U)         /*!< Bit position for SIM_SCGC6_DSPI1. */
#define BM_SIM_SCGC6_DSPI1   (0x00002000U) /*!< Bit mask for SIM_SCGC6_DSPI1. */
#define BS_SIM_SCGC6_DSPI1   (1U)          /*!< Bit field size in bits for SIM_SCGC6_DSPI1. */

/*! @brief Read current value of the SIM_SCGC6_DSPI1 field. */
#define BR_SIM_SCGC6_DSPI1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DSPI1))

/*! @brief Format value for bitfield SIM_SCGC6_DSPI1. */
#define BF_SIM_SCGC6_DSPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DSPI1) & BM_SIM_SCGC6_DSPI1)

/*! @brief Set the DSPI1 field to a new value. */
#define BW_SIM_SCGC6_DSPI1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DSPI1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field SAI0[15] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_SAI0    (15U)         /*!< Bit position for SIM_SCGC6_SAI0. */
#define BM_SIM_SCGC6_SAI0    (0x00008000U) /*!< Bit mask for SIM_SCGC6_SAI0. */
#define BS_SIM_SCGC6_SAI0    (1U)          /*!< Bit field size in bits for SIM_SCGC6_SAI0. */

/*! @brief Read current value of the SIM_SCGC6_SAI0 field. */
#define BR_SIM_SCGC6_SAI0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SAI0))

/*! @brief Format value for bitfield SIM_SCGC6_SAI0. */
#define BF_SIM_SCGC6_SAI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SAI0) & BM_SIM_SCGC6_SAI0)

/*! @brief Set the SAI0 field to a new value. */
#define BW_SIM_SCGC6_SAI0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SAI0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field CRC[18] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_CRC     (18U)         /*!< Bit position for SIM_SCGC6_CRC. */
#define BM_SIM_SCGC6_CRC     (0x00040000U) /*!< Bit mask for SIM_SCGC6_CRC. */
#define BS_SIM_SCGC6_CRC     (1U)          /*!< Bit field size in bits for SIM_SCGC6_CRC. */

/*! @brief Read current value of the SIM_SCGC6_CRC field. */
#define BR_SIM_SCGC6_CRC(x)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC))

/*! @brief Format value for bitfield SIM_SCGC6_CRC. */
#define BF_SIM_SCGC6_CRC(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC)

/*! @brief Set the CRC field to a new value. */
#define BW_SIM_SCGC6_CRC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field USBHS[20] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_USBHS   (20U)         /*!< Bit position for SIM_SCGC6_USBHS. */
#define BM_SIM_SCGC6_USBHS   (0x00100000U) /*!< Bit mask for SIM_SCGC6_USBHS. */
#define BS_SIM_SCGC6_USBHS   (1U)          /*!< Bit field size in bits for SIM_SCGC6_USBHS. */

/*! @brief Read current value of the SIM_SCGC6_USBHS field. */
#define BR_SIM_SCGC6_USBHS(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBHS))

/*! @brief Format value for bitfield SIM_SCGC6_USBHS. */
#define BF_SIM_SCGC6_USBHS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_USBHS) & BM_SIM_SCGC6_USBHS)

/*! @brief Set the USBHS field to a new value. */
#define BW_SIM_SCGC6_USBHS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBHS) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field USBDCD[21] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_USBDCD  (21U)         /*!< Bit position for SIM_SCGC6_USBDCD. */
#define BM_SIM_SCGC6_USBDCD  (0x00200000U) /*!< Bit mask for SIM_SCGC6_USBDCD. */
#define BS_SIM_SCGC6_USBDCD  (1U)          /*!< Bit field size in bits for SIM_SCGC6_USBDCD. */

/*! @brief Read current value of the SIM_SCGC6_USBDCD field. */
#define BR_SIM_SCGC6_USBDCD(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD))

/*! @brief Format value for bitfield SIM_SCGC6_USBDCD. */
#define BF_SIM_SCGC6_USBDCD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_USBDCD) & BM_SIM_SCGC6_USBDCD)

/*! @brief Set the USBDCD field to a new value. */
#define BW_SIM_SCGC6_USBDCD(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field PDB[22] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_PDB     (22U)         /*!< Bit position for SIM_SCGC6_PDB. */
#define BM_SIM_SCGC6_PDB     (0x00400000U) /*!< Bit mask for SIM_SCGC6_PDB. */
#define BS_SIM_SCGC6_PDB     (1U)          /*!< Bit field size in bits for SIM_SCGC6_PDB. */

/*! @brief Read current value of the SIM_SCGC6_PDB field. */
#define BR_SIM_SCGC6_PDB(x)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB))

/*! @brief Format value for bitfield SIM_SCGC6_PDB. */
#define BF_SIM_SCGC6_PDB(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB)

/*! @brief Set the PDB field to a new value. */
#define BW_SIM_SCGC6_PDB(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field PIT[23] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_PIT     (23U)         /*!< Bit position for SIM_SCGC6_PIT. */
#define BM_SIM_SCGC6_PIT     (0x00800000U) /*!< Bit mask for SIM_SCGC6_PIT. */
#define BS_SIM_SCGC6_PIT     (1U)          /*!< Bit field size in bits for SIM_SCGC6_PIT. */

/*! @brief Read current value of the SIM_SCGC6_PIT field. */
#define BR_SIM_SCGC6_PIT(x)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT))

/*! @brief Format value for bitfield SIM_SCGC6_PIT. */
#define BF_SIM_SCGC6_PIT(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT)

/*! @brief Set the PIT field to a new value. */
#define BW_SIM_SCGC6_PIT(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field FTM0[24] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_FTM0    (24U)         /*!< Bit position for SIM_SCGC6_FTM0. */
#define BM_SIM_SCGC6_FTM0    (0x01000000U) /*!< Bit mask for SIM_SCGC6_FTM0. */
#define BS_SIM_SCGC6_FTM0    (1U)          /*!< Bit field size in bits for SIM_SCGC6_FTM0. */

/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
#define BR_SIM_SCGC6_FTM0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0))

/*! @brief Format value for bitfield SIM_SCGC6_FTM0. */
#define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0)

/*! @brief Set the FTM0 field to a new value. */
#define BW_SIM_SCGC6_FTM0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field FTM1[25] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_FTM1    (25U)         /*!< Bit position for SIM_SCGC6_FTM1. */
#define BM_SIM_SCGC6_FTM1    (0x02000000U) /*!< Bit mask for SIM_SCGC6_FTM1. */
#define BS_SIM_SCGC6_FTM1    (1U)          /*!< Bit field size in bits for SIM_SCGC6_FTM1. */

/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
#define BR_SIM_SCGC6_FTM1(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1))

/*! @brief Format value for bitfield SIM_SCGC6_FTM1. */
#define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1)

/*! @brief Set the FTM1 field to a new value. */
#define BW_SIM_SCGC6_FTM1(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field ADC0[27] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_ADC0    (27U)         /*!< Bit position for SIM_SCGC6_ADC0. */
#define BM_SIM_SCGC6_ADC0    (0x08000000U) /*!< Bit mask for SIM_SCGC6_ADC0. */
#define BS_SIM_SCGC6_ADC0    (1U)          /*!< Bit field size in bits for SIM_SCGC6_ADC0. */

/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
#define BR_SIM_SCGC6_ADC0(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0))

/*! @brief Format value for bitfield SIM_SCGC6_ADC0. */
#define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0)

/*! @brief Set the ADC0 field to a new value. */
#define BW_SIM_SCGC6_ADC0(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field ADC2[28] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_ADC2    (28U)         /*!< Bit position for SIM_SCGC6_ADC2. */
#define BM_SIM_SCGC6_ADC2    (0x10000000U) /*!< Bit mask for SIM_SCGC6_ADC2. */
#define BS_SIM_SCGC6_ADC2    (1U)          /*!< Bit field size in bits for SIM_SCGC6_ADC2. */

/*! @brief Read current value of the SIM_SCGC6_ADC2 field. */
#define BR_SIM_SCGC6_ADC2(x) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC2))

/*! @brief Format value for bitfield SIM_SCGC6_ADC2. */
#define BF_SIM_SCGC6_ADC2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC2) & BM_SIM_SCGC6_ADC2)

/*! @brief Set the ADC2 field to a new value. */
#define BW_SIM_SCGC6_ADC2(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC2) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC6, field RTC[29] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC6_RTC     (29U)         /*!< Bit position for SIM_SCGC6_RTC. */
#define BM_SIM_SCGC6_RTC     (0x20000000U) /*!< Bit mask for SIM_SCGC6_RTC. */
#define BS_SIM_SCGC6_RTC     (1U)          /*!< Bit field size in bits for SIM_SCGC6_RTC. */

/*! @brief Read current value of the SIM_SCGC6_RTC field. */
#define BR_SIM_SCGC6_RTC(x)  (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC))

/*! @brief Format value for bitfield SIM_SCGC6_RTC. */
#define BF_SIM_SCGC6_RTC(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC)

/*! @brief Set the RTC field to a new value. */
#define BW_SIM_SCGC6_RTC(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_SCGC7 - System Clock Gating Control Register 7
 ******************************************************************************/

/*!
 * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
 *
 * Reset value: 0x00000007U
 */
typedef union _hw_sim_scgc7
{
    uint32_t U;
    struct _hw_sim_scgc7_bitfields
    {
        uint32_t FLEXBUS : 1;          /*!< [0] FlexBus controller clock gate control
                                        * */
        uint32_t DMA : 1;              /*!< [1] DMA controller clock gate control */
        uint32_t MPUb : 1;             /*!< [2] MPU clock gate control */
        uint32_t RESERVED0 : 29;       /*!< [31:3]  */
    } B;
} hw_sim_scgc7_t;

/*!
 * @name Constants and macros for entire SIM_SCGC7 register
 */
/*@{*/
#define HW_SIM_SCGC7_ADDR(x)     ((x) + 0x1040U)

#define HW_SIM_SCGC7(x)          (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR(x))
#define HW_SIM_SCGC7_RD(x)       (HW_SIM_SCGC7(x).U)
#define HW_SIM_SCGC7_WR(x, v)    (HW_SIM_SCGC7(x).U = (v))
#define HW_SIM_SCGC7_SET(x, v)   (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) |  (v)))
#define HW_SIM_SCGC7_CLR(x, v)   (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v)))
#define HW_SIM_SCGC7_TOG(x, v)   (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_SCGC7 bitfields
 */

/*!
 * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC7_FLEXBUS (0U)          /*!< Bit position for SIM_SCGC7_FLEXBUS. */
#define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /*!< Bit mask for SIM_SCGC7_FLEXBUS. */
#define BS_SIM_SCGC7_FLEXBUS (1U)          /*!< Bit field size in bits for SIM_SCGC7_FLEXBUS. */

/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
#define BR_SIM_SCGC7_FLEXBUS(x) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS))

/*! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. */
#define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS)

/*! @brief Set the FLEXBUS field to a new value. */
#define BW_SIM_SCGC7_FLEXBUS(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC7, field DMA[1] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC7_DMA     (1U)          /*!< Bit position for SIM_SCGC7_DMA. */
#define BM_SIM_SCGC7_DMA     (0x00000002U) /*!< Bit mask for SIM_SCGC7_DMA. */
#define BS_SIM_SCGC7_DMA     (1U)          /*!< Bit field size in bits for SIM_SCGC7_DMA. */

/*! @brief Read current value of the SIM_SCGC7_DMA field. */
#define BR_SIM_SCGC7_DMA(x)  (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA))

/*! @brief Format value for bitfield SIM_SCGC7_DMA. */
#define BF_SIM_SCGC7_DMA(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA)

/*! @brief Set the DMA field to a new value. */
#define BW_SIM_SCGC7_DMA(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA) = (v))
/*@}*/

/*!
 * @name Register SIM_SCGC7, field MPU[2] (RW)
 *
 * Values:
 * - 0 - Clock is disabled.
 * - 1 - Clock is enabled.
 */
/*@{*/
#define BP_SIM_SCGC7_MPU     (2U)          /*!< Bit position for SIM_SCGC7_MPU. */
#define BM_SIM_SCGC7_MPU     (0x00000004U) /*!< Bit mask for SIM_SCGC7_MPU. */
#define BS_SIM_SCGC7_MPU     (1U)          /*!< Bit field size in bits for SIM_SCGC7_MPU. */

/*! @brief Read current value of the SIM_SCGC7_MPU field. */
#define BR_SIM_SCGC7_MPU(x)  (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU))

/*! @brief Format value for bitfield SIM_SCGC7_MPU. */
#define BF_SIM_SCGC7_MPU(v)  ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_MPU) & BM_SIM_SCGC7_MPU)

/*! @brief Set the MPU field to a new value. */
#define BW_SIM_SCGC7_MPU(x, v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU) = (v))
/*@}*/

/*******************************************************************************
 * HW_SIM_CLKDIV1 - System Clock Divider Register 1
 ******************************************************************************/

/*!
 * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
 *
 * Reset value: 0x00000000U
 *
 * The CLKDIV1 register cannot be written to when the device is in VLPR mode.
 * The OUTDIV[1:4] bitfields reset only for power-on reset and are unaffected by
 * other reset types.
 */
typedef union _hw_sim_clkdiv1
{
    uint32_t U;
    struct _hw_sim_clkdiv1_bitfields
    {
        uint32_t RESERVED0 : 16;       /*!< [15:0]  */
        uint32_t OUTDIV4 : 4;          /*!< [19:16] Clock 4 output divider value */
        uint32_t OUTDIV3 : 4;          /*!< [23:20] Clock 3 output divider value */
        uint32_t OUTDIV2 : 4;          /*!< [27:24] Clock 2 output divider value */
        uint32_t OUTDIV1 : 4;          /*!< [31:28] Clock 1 output divider value */
    } B;
} hw_sim_clkdiv1_t;

/*!
 * @name Constants and macros for entire SIM_CLKDIV1 register
 */
/*@{*/
#define HW_SIM_CLKDIV1_ADDR(x)   ((x) + 0x1044U)

#define HW_SIM_CLKDIV1(x)        (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR(x))
#define HW_SIM_CLKDIV1_RD(x)     (HW_SIM_CLKDIV1(x).U)
#define HW_SIM_CLKDIV1_WR(x, v)  (HW_SIM_CLKDIV1(x).U = (v))
#define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) |  (v)))
#define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v)))
#define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_CLKDIV1 bitfields
 */

/*!
 * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
 *
 * This field sets the divide value for the flash clock. At the end of reset, it
 * is loaded with either 0001 or 1111 depending on FTFE_FOPT[LPBOOT].
 *
 * Values:
 * - 0000 - Divide-by-1.
 * - 0001 - Divide-by-2.
 * - 0010 - Divide-by-3.
 * - 0011 - Divide-by-4.
 * - 0100 - Divide-by-5.
 * - 0101 - Divide-by-6.
 * - 0110 - Divide-by-7.
 * - 0111 - Divide-by-8.
 * - 1000 - Divide-by-9.
 * - 1001 - Divide-by-10.
 * - 1010 - Divide-by-11.
 * - 1011 - Divide-by-12.
 * - 1100 - Divide-by-13.
 * - 1101 - Divide-by-14.
 * - 1110 - Divide-by-15.
 * - 1111 - Divide-by-16.
 */
/*@{*/
#define BP_SIM_CLKDIV1_OUTDIV4 (16U)       /*!< Bit position for SIM_CLKDIV1_OUTDIV4. */
#define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV4. */
#define BS_SIM_CLKDIV1_OUTDIV4 (4U)        /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. */

/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
#define BR_SIM_CLKDIV1_OUTDIV4(x) (HW_SIM_CLKDIV1(x).B.OUTDIV4)

/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. */
#define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4)

/*! @brief Set the OUTDIV4 field to a new value. */
#define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v)))
/*@}*/

/*!
 * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
 *
 * This field sets the divide value for the FlexBus clock driven to the external
 * pin (FB_CLK). At the end of reset, it is loaded with either 0001 or 1111
 * depending on FTFE_FOPT[LPBOOT].
 *
 * Values:
 * - 0000 - Divide-by-1.
 * - 0001 - Divide-by-2.
 * - 0010 - Divide-by-3.
 * - 0011 - Divide-by-4.
 * - 0100 - Divide-by-5.
 * - 0101 - Divide-by-6.
 * - 0110 - Divide-by-7.
 * - 0111 - Divide-by-8.
 * - 1000 - Divide-by-9.
 * - 1001 - Divide-by-10.
 * - 1010 - Divide-by-11.
 * - 1011 - Divide-by-12.
 * - 1100 - Divide-by-13.
 * - 1101 - Divide-by-14.
 * - 1110 - Divide-by-15.
 * - 1111 - Divide-by-16.
 */
/*@{*/
#define BP_SIM_CLKDIV1_OUTDIV3 (20U)       /*!< Bit position for SIM_CLKDIV1_OUTDIV3. */
#define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV3. */
#define BS_SIM_CLKDIV1_OUTDIV3 (4U)        /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. */

/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
#define BR_SIM_CLKDIV1_OUTDIV3(x) (HW_SIM_CLKDIV1(x).B.OUTDIV3)

/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. */
#define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3)

/*! @brief Set the OUTDIV3 field to a new value. */
#define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v)))
/*@}*/

/*!
 * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
 *
 * This field sets the divide value for the peripheral clock. At the end of
 * reset, it is loaded with either 0000 or 0111 depending on FTFE_FOPT[LPBOOT].
 *
 * Values:
 * - 0000 - Divide-by-1.
 * - 0001 - Divide-by-2.
 * - 0010 - Divide-by-3.
 * - 0011 - Divide-by-4.
 * - 0100 - Divide-by-5.
 * - 0101 - Divide-by-6.
 * - 0110 - Divide-by-7.
 * - 0111 - Divide-by-8.
 * - 1000 - Divide-by-9.
 * - 1001 - Divide-by-10.
 * - 1010 - Divide-by-11.
 * - 1011 - Divide-by-12.
 * - 1100 - Divide-by-13.
 * - 1101 - Divide-by-14.
 * - 1110 - Divide-by-15.
 * - 1111 - Divide-by-16.
 */
/*@{*/
#define BP_SIM_CLKDIV1_OUTDIV2 (24U)       /*!< Bit position for SIM_CLKDIV1_OUTDIV2. */
#define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV2. */
#define BS_SIM_CLKDIV1_OUTDIV2 (4U)        /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. */

/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
#define BR_SIM_CLKDIV1_OUTDIV2(x) (HW_SIM_CLKDIV1(x).B.OUTDIV2)

/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. */
#define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2)

/*! @brief Set the OUTDIV2 field to a new value. */
#define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v)))
/*@}*/

/*!
 * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
 *
 * This field sets the divide value for the core/system clock. At the end of
 * reset, it is loaded with either 0000 or 0111 depending on FTFE_FOPT[LPBOOT].
 *
 * Values:
 * - 0000 - Divide-by-1.
 * - 0001 - Divide-by-2.
 * - 0010 - Divide-by-3.
 * - 0011 - Divide-by-4.
 * - 0100 - Divide-by-5.
 * - 0101 - Divide-by-6.
 * - 0110 - Divide-by-7.
 * - 0111 - Divide-by-8.
 * - 1000 - Divide-by-9.
 * - 1001 - Divide-by-10.
 * - 1010 - Divide-by-11.
 * - 1011 - Divide-by-12.
 * - 1100 - Divide-by-13.
 * - 1101 - Divide-by-14.
 * - 1110 - Divide-by-15.
 * - 1111 - Divide-by-16.
 */
/*@{*/
#define BP_SIM_CLKDIV1_OUTDIV1 (28U)       /*!< Bit position for SIM_CLKDIV1_OUTDIV1. */
#define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV1. */
#define BS_SIM_CLKDIV1_OUTDIV1 (4U)        /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. */

/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
#define BR_SIM_CLKDIV1_OUTDIV1(x) (HW_SIM_CLKDIV1(x).B.OUTDIV1)

/*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. */
#define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1)

/*! @brief Set the OUTDIV1 field to a new value. */
#define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v)))
/*@}*/

/*******************************************************************************
 * HW_SIM_CLKDIV2 - System Clock Divider Register 2
 ******************************************************************************/

/*!
 * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_clkdiv2
{
    uint32_t U;
    struct _hw_sim_clkdiv2_bitfields
    {
        uint32_t USBFSFRAC : 1;        /*!< [0] USB FS clock divider fraction */
        uint32_t USBFSDIV : 3;         /*!< [3:1] USB FS clock divider divisor */
        uint32_t RESERVED0 : 4;        /*!< [7:4]  */
        uint32_t USBHSFRAC : 1;        /*!< [8] USB HS clock divider fraction */
        uint32_t USBHSDIV : 3;         /*!< [11:9] USB HS clock divider divisor */
        uint32_t RESERVED1 : 20;       /*!< [31:12]  */
    } B;
} hw_sim_clkdiv2_t;

/*!
 * @name Constants and macros for entire SIM_CLKDIV2 register
 */
/*@{*/
#define HW_SIM_CLKDIV2_ADDR(x)   ((x) + 0x1048U)

#define HW_SIM_CLKDIV2(x)        (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR(x))
#define HW_SIM_CLKDIV2_RD(x)     (HW_SIM_CLKDIV2(x).U)
#define HW_SIM_CLKDIV2_WR(x, v)  (HW_SIM_CLKDIV2(x).U = (v))
#define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) |  (v)))
#define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v)))
#define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_CLKDIV2 bitfields
 */

/*!
 * @name Register SIM_CLKDIV2, field USBFSFRAC[0] (RW)
 *
 * This field sets the fraction multiply value for the fractional clock divider
 * used as a USB clock source (SOPT2[USBFSRC] = 1). Divider output clock =
 * Divider input clock * [(USBFSFRAC+1) / (USBFSDIV+1)]
 */
/*@{*/
#define BP_SIM_CLKDIV2_USBFSFRAC (0U)      /*!< Bit position for SIM_CLKDIV2_USBFSFRAC. */
#define BM_SIM_CLKDIV2_USBFSFRAC (0x00000001U) /*!< Bit mask for SIM_CLKDIV2_USBFSFRAC. */
#define BS_SIM_CLKDIV2_USBFSFRAC (1U)      /*!< Bit field size in bits for SIM_CLKDIV2_USBFSFRAC. */

/*! @brief Read current value of the SIM_CLKDIV2_USBFSFRAC field. */
#define BR_SIM_CLKDIV2_USBFSFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFSFRAC))

/*! @brief Format value for bitfield SIM_CLKDIV2_USBFSFRAC. */
#define BF_SIM_CLKDIV2_USBFSFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFSFRAC) & BM_SIM_CLKDIV2_USBFSFRAC)

/*! @brief Set the USBFSFRAC field to a new value. */
#define BW_SIM_CLKDIV2_USBFSFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFSFRAC) = (v))
/*@}*/

/*!
 * @name Register SIM_CLKDIV2, field USBFSDIV[3:1] (RW)
 *
 * This field sets the divide value for the fractional clock divider used as a
 * USB clock source (SOPT2[USBFSRC] = 1). Divider output clock = Divider input
 * clock * [(USBFSFRAC+1) / (USBFSDIV+1)]
 */
/*@{*/
#define BP_SIM_CLKDIV2_USBFSDIV (1U)       /*!< Bit position for SIM_CLKDIV2_USBFSDIV. */
#define BM_SIM_CLKDIV2_USBFSDIV (0x0000000EU) /*!< Bit mask for SIM_CLKDIV2_USBFSDIV. */
#define BS_SIM_CLKDIV2_USBFSDIV (3U)       /*!< Bit field size in bits for SIM_CLKDIV2_USBFSDIV. */

/*! @brief Read current value of the SIM_CLKDIV2_USBFSDIV field. */
#define BR_SIM_CLKDIV2_USBFSDIV(x) (HW_SIM_CLKDIV2(x).B.USBFSDIV)

/*! @brief Format value for bitfield SIM_CLKDIV2_USBFSDIV. */
#define BF_SIM_CLKDIV2_USBFSDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFSDIV) & BM_SIM_CLKDIV2_USBFSDIV)

/*! @brief Set the USBFSDIV field to a new value. */
#define BW_SIM_CLKDIV2_USBFSDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBFSDIV) | BF_SIM_CLKDIV2_USBFSDIV(v)))
/*@}*/

/*!
 * @name Register SIM_CLKDIV2, field USBHSFRAC[8] (RW)
 *
 * This field sets the fraction multiply value for the fractional clock divider
 * used as a USB clock source (SOPT2[USBHSRC] = 1). Divider output clock =
 * Divider input clock * [(USBHSFRAC+1) / (USBHSDIV+1)]
 */
/*@{*/
#define BP_SIM_CLKDIV2_USBHSFRAC (8U)      /*!< Bit position for SIM_CLKDIV2_USBHSFRAC. */
#define BM_SIM_CLKDIV2_USBHSFRAC (0x00000100U) /*!< Bit mask for SIM_CLKDIV2_USBHSFRAC. */
#define BS_SIM_CLKDIV2_USBHSFRAC (1U)      /*!< Bit field size in bits for SIM_CLKDIV2_USBHSFRAC. */

/*! @brief Read current value of the SIM_CLKDIV2_USBHSFRAC field. */
#define BR_SIM_CLKDIV2_USBHSFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBHSFRAC))

/*! @brief Format value for bitfield SIM_CLKDIV2_USBHSFRAC. */
#define BF_SIM_CLKDIV2_USBHSFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBHSFRAC) & BM_SIM_CLKDIV2_USBHSFRAC)

/*! @brief Set the USBHSFRAC field to a new value. */
#define BW_SIM_CLKDIV2_USBHSFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBHSFRAC) = (v))
/*@}*/

/*!
 * @name Register SIM_CLKDIV2, field USBHSDIV[11:9] (RW)
 *
 * This field sets the divide value for the fractional clock divider used as a
 * USB clock source (SOPT2[USBHSRC] = 1). Divider output clock = Divider input
 * clock * [(USBHSFRAC+1) / (USBHSDIV+1)]
 */
/*@{*/
#define BP_SIM_CLKDIV2_USBHSDIV (9U)       /*!< Bit position for SIM_CLKDIV2_USBHSDIV. */
#define BM_SIM_CLKDIV2_USBHSDIV (0x00000E00U) /*!< Bit mask for SIM_CLKDIV2_USBHSDIV. */
#define BS_SIM_CLKDIV2_USBHSDIV (3U)       /*!< Bit field size in bits for SIM_CLKDIV2_USBHSDIV. */

/*! @brief Read current value of the SIM_CLKDIV2_USBHSDIV field. */
#define BR_SIM_CLKDIV2_USBHSDIV(x) (HW_SIM_CLKDIV2(x).B.USBHSDIV)

/*! @brief Format value for bitfield SIM_CLKDIV2_USBHSDIV. */
#define BF_SIM_CLKDIV2_USBHSDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBHSDIV) & BM_SIM_CLKDIV2_USBHSDIV)

/*! @brief Set the USBHSDIV field to a new value. */
#define BW_SIM_CLKDIV2_USBHSDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBHSDIV) | BF_SIM_CLKDIV2_USBHSDIV(v)))
/*@}*/

/*******************************************************************************
 * HW_SIM_FCFG1 - Flash Configuration Register 1
 ******************************************************************************/

/*!
 * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_fcfg1
{
    uint32_t U;
    struct _hw_sim_fcfg1_bitfields
    {
        uint32_t FTFDIS : 1;           /*!< [0] Disable FTFE */
        uint32_t RESERVED0 : 7;        /*!< [7:1]  */
        uint32_t DEPART : 4;           /*!< [11:8] FlexNVM partition */
        uint32_t RESERVED1 : 4;        /*!< [15:12]  */
        uint32_t EESIZE : 4;           /*!< [19:16] EEPROM size */
        uint32_t RESERVED2 : 4;        /*!< [23:20]  */
        uint32_t PFSIZE : 4;           /*!< [27:24] Program flash size */
        uint32_t NVMSIZE : 4;          /*!< [31:28] FlexNVM size */
    } B;
} hw_sim_fcfg1_t;

/*!
 * @name Constants and macros for entire SIM_FCFG1 register
 */
/*@{*/
#define HW_SIM_FCFG1_ADDR(x)     ((x) + 0x104CU)

#define HW_SIM_FCFG1(x)          (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR(x))
#define HW_SIM_FCFG1_RD(x)       (HW_SIM_FCFG1(x).U)
#define HW_SIM_FCFG1_WR(x, v)    (HW_SIM_FCFG1(x).U = (v))
#define HW_SIM_FCFG1_SET(x, v)   (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) |  (v)))
#define HW_SIM_FCFG1_CLR(x, v)   (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v)))
#define HW_SIM_FCFG1_TOG(x, v)   (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_FCFG1 bitfields
 */

/*!
 * @name Register SIM_FCFG1, field FTFDIS[0] (RW)
 */
/*@{*/
#define BP_SIM_FCFG1_FTFDIS  (0U)          /*!< Bit position for SIM_FCFG1_FTFDIS. */
#define BM_SIM_FCFG1_FTFDIS  (0x00000001U) /*!< Bit mask for SIM_FCFG1_FTFDIS. */
#define BS_SIM_FCFG1_FTFDIS  (1U)          /*!< Bit field size in bits for SIM_FCFG1_FTFDIS. */

/*! @brief Read current value of the SIM_FCFG1_FTFDIS field. */
#define BR_SIM_FCFG1_FTFDIS(x) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FTFDIS))

/*! @brief Format value for bitfield SIM_FCFG1_FTFDIS. */
#define BF_SIM_FCFG1_FTFDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FTFDIS) & BM_SIM_FCFG1_FTFDIS)

/*! @brief Set the FTFDIS field to a new value. */
#define BW_SIM_FCFG1_FTFDIS(x, v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FTFDIS) = (v))
/*@}*/

/*!
 * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
 *
 * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
 * description in FTFE chapter. For devices without FlexNVM: Reserved
 */
/*@{*/
#define BP_SIM_FCFG1_DEPART  (8U)          /*!< Bit position for SIM_FCFG1_DEPART. */
#define BM_SIM_FCFG1_DEPART  (0x00000F00U) /*!< Bit mask for SIM_FCFG1_DEPART. */
#define BS_SIM_FCFG1_DEPART  (4U)          /*!< Bit field size in bits for SIM_FCFG1_DEPART. */

/*! @brief Read current value of the SIM_FCFG1_DEPART field. */
#define BR_SIM_FCFG1_DEPART(x) (HW_SIM_FCFG1(x).B.DEPART)
/*@}*/

/*!
 * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
 *
 * EEPROM data size .
 *
 * Values:
 * - 0000 - 16 KB
 * - 0001 - 8 KB
 * - 0010 - 4 KB
 * - 0011 - 2 KB
 * - 0100 - 1 KB
 * - 0101 - 512 Bytes
 * - 0110 - 256 Bytes
 * - 0111 - 128 Bytes
 * - 1000 - 64 Bytes
 * - 1001 - 32 Bytes
 * - 1111 - 0 Bytes
 */
/*@{*/
#define BP_SIM_FCFG1_EESIZE  (16U)         /*!< Bit position for SIM_FCFG1_EESIZE. */
#define BM_SIM_FCFG1_EESIZE  (0x000F0000U) /*!< Bit mask for SIM_FCFG1_EESIZE. */
#define BS_SIM_FCFG1_EESIZE  (4U)          /*!< Bit field size in bits for SIM_FCFG1_EESIZE. */

/*! @brief Read current value of the SIM_FCFG1_EESIZE field. */
#define BR_SIM_FCFG1_EESIZE(x) (HW_SIM_FCFG1(x).B.EESIZE)
/*@}*/

/*!
 * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
 *
 * This field specifies the amount of program flash memory available on the
 * device .
 *
 * Values:
 * - 0000 - Reserved
 * - 0001 - Reserved
 * - 0010 - Reserved
 * - 0011 - Reserved
 * - 0100 - Reserved
 * - 0101 - Reserved
 * - 0110 - Reserved
 * - 0111 - Reserved
 * - 1000 - Reserved
 * - 1001 - Reserved
 * - 1010 - Reserved
 * - 1011 - 512 KB, 16 KB protection size
 * - 1100 - Reserved
 * - 1101 - 1024 KB, 32 KB protection size
 * - 1110 - Reserved
 * - 1111 - 1024 KB, 32 KB protection size
 */
/*@{*/
#define BP_SIM_FCFG1_PFSIZE  (24U)         /*!< Bit position for SIM_FCFG1_PFSIZE. */
#define BM_SIM_FCFG1_PFSIZE  (0x0F000000U) /*!< Bit mask for SIM_FCFG1_PFSIZE. */
#define BS_SIM_FCFG1_PFSIZE  (4U)          /*!< Bit field size in bits for SIM_FCFG1_PFSIZE. */

/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
#define BR_SIM_FCFG1_PFSIZE(x) (HW_SIM_FCFG1(x).B.PFSIZE)
/*@}*/

/*!
 * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
 *
 * This field specifies the amount of FlexNVM memory available on the device .
 *
 * Values:
 * - 0000 - 0 KB
 * - 0001 - Reserved
 * - 0010 - Reserved
 * - 0011 - Reserved
 * - 0100 - Reserved
 * - 0101 - Reserved
 * - 0110 - Reserved
 * - 0111 - Reserved
 * - 1000 - Reserved
 * - 1001 - Reserved
 * - 1010 - Reserved
 * - 1011 - 512 KB, 16 KB protection region
 * - 1100 - Reserved
 * - 1101 - Reserved
 * - 1110 - Reserved
 * - 1111 - 512 KB, 16 KB protection region
 */
/*@{*/
#define BP_SIM_FCFG1_NVMSIZE (28U)         /*!< Bit position for SIM_FCFG1_NVMSIZE. */
#define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) /*!< Bit mask for SIM_FCFG1_NVMSIZE. */
#define BS_SIM_FCFG1_NVMSIZE (4U)          /*!< Bit field size in bits for SIM_FCFG1_NVMSIZE. */

/*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */
#define BR_SIM_FCFG1_NVMSIZE(x) (HW_SIM_FCFG1(x).B.NVMSIZE)
/*@}*/

/*******************************************************************************
 * HW_SIM_FCFG2 - Flash Configuration Register 2
 ******************************************************************************/

/*!
 * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_fcfg2
{
    uint32_t U;
    struct _hw_sim_fcfg2_bitfields
    {
        uint32_t RESERVED0 : 16;       /*!< [15:0]  */
        uint32_t MAXADDR23 : 6;        /*!< [21:16] Max address block 2 or 3 */
        uint32_t RESERVED1 : 2;        /*!< [23:22]  */
        uint32_t MAXADDR01 : 6;        /*!< [29:24] Max address block 0 or 1 */
        uint32_t RESERVED2 : 2;        /*!< [31:30]  */
    } B;
} hw_sim_fcfg2_t;

/*!
 * @name Constants and macros for entire SIM_FCFG2 register
 */
/*@{*/
#define HW_SIM_FCFG2_ADDR(x)     ((x) + 0x1050U)

#define HW_SIM_FCFG2(x)          (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR(x))
#define HW_SIM_FCFG2_RD(x)       (HW_SIM_FCFG2(x).U)
/*@}*/

/*
 * Constants & macros for individual SIM_FCFG2 bitfields
 */

/*!
 * @name Register SIM_FCFG2, field MAXADDR23[21:16] (RO)
 *
 * For devices with FlexNVM: This field concatenated with 13 zeros plus the
 * FlexNVM base address indicates the number of 8 KB regions in logically interleaved
 * FlexNVM blocks 2 or 3. For example, relative FlexNVM byte addresses below
 * {MAXADDR23,13'b0} are valid for block 2 while byte addresses at or above
 * {MAXADDR23,13'b0} and below {2*MAXADDR23,13'b0} are valid block 3. For devices with
 * program flash only: This field concatenated with 13 zeros plus the value of the
 * MAXADDR01 field indicates the number of 8 KB regions in logically interleaved
 * program flash blocks 2 or 3. For example, relative P-Flash byte addresses at
 * or above {2*MAXADDR01,13'b0} and below {2*MAXADDR01+MAXADDR23,13'b0} are valid
 * for block 2 while byte addresses at or above {2*MAXADDR01+MAXADDR23,13'b0} and
 * below {2*MAXADDR01+2*MAXADDR23,13'b0} are valid for block 3.
 */
/*@{*/
#define BP_SIM_FCFG2_MAXADDR23 (16U)       /*!< Bit position for SIM_FCFG2_MAXADDR23. */
#define BM_SIM_FCFG2_MAXADDR23 (0x003F0000U) /*!< Bit mask for SIM_FCFG2_MAXADDR23. */
#define BS_SIM_FCFG2_MAXADDR23 (6U)        /*!< Bit field size in bits for SIM_FCFG2_MAXADDR23. */

/*! @brief Read current value of the SIM_FCFG2_MAXADDR23 field. */
#define BR_SIM_FCFG2_MAXADDR23(x) (HW_SIM_FCFG2(x).B.MAXADDR23)
/*@}*/

/*!
 * @name Register SIM_FCFG2, field MAXADDR01[29:24] (RO)
 *
 * This field concatenated with 13 zeros indicates the number of 8 KB regions in
 * logically interleaved program plash blocks 0 or 1.
 */
/*@{*/
#define BP_SIM_FCFG2_MAXADDR01 (24U)       /*!< Bit position for SIM_FCFG2_MAXADDR01. */
#define BM_SIM_FCFG2_MAXADDR01 (0x3F000000U) /*!< Bit mask for SIM_FCFG2_MAXADDR01. */
#define BS_SIM_FCFG2_MAXADDR01 (6U)        /*!< Bit field size in bits for SIM_FCFG2_MAXADDR01. */

/*! @brief Read current value of the SIM_FCFG2_MAXADDR01 field. */
#define BR_SIM_FCFG2_MAXADDR01(x) (HW_SIM_FCFG2(x).B.MAXADDR01)
/*@}*/

/*******************************************************************************
 * HW_SIM_UIDH - Unique Identification Register High
 ******************************************************************************/

/*!
 * @brief HW_SIM_UIDH - Unique Identification Register High (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_uidh
{
    uint32_t U;
    struct _hw_sim_uidh_bitfields
    {
        uint32_t UID : 32;             /*!< [31:0] Unique Identification */
    } B;
} hw_sim_uidh_t;

/*!
 * @name Constants and macros for entire SIM_UIDH register
 */
/*@{*/
#define HW_SIM_UIDH_ADDR(x)      ((x) + 0x1054U)

#define HW_SIM_UIDH(x)           (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR(x))
#define HW_SIM_UIDH_RD(x)        (HW_SIM_UIDH(x).U)
/*@}*/

/*
 * Constants & macros for individual SIM_UIDH bitfields
 */

/*!
 * @name Register SIM_UIDH, field UID[31:0] (RO)
 *
 * Unique identification for the device.
 */
/*@{*/
#define BP_SIM_UIDH_UID      (0U)          /*!< Bit position for SIM_UIDH_UID. */
#define BM_SIM_UIDH_UID      (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDH_UID. */
#define BS_SIM_UIDH_UID      (32U)         /*!< Bit field size in bits for SIM_UIDH_UID. */

/*! @brief Read current value of the SIM_UIDH_UID field. */
#define BR_SIM_UIDH_UID(x)   (HW_SIM_UIDH(x).U)
/*@}*/

/*******************************************************************************
 * HW_SIM_UIDMH - Unique Identification Register Mid-High
 ******************************************************************************/

/*!
 * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_uidmh
{
    uint32_t U;
    struct _hw_sim_uidmh_bitfields
    {
        uint32_t UID : 32;             /*!< [31:0] Unique Identification */
    } B;
} hw_sim_uidmh_t;

/*!
 * @name Constants and macros for entire SIM_UIDMH register
 */
/*@{*/
#define HW_SIM_UIDMH_ADDR(x)     ((x) + 0x1058U)

#define HW_SIM_UIDMH(x)          (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR(x))
#define HW_SIM_UIDMH_RD(x)       (HW_SIM_UIDMH(x).U)
/*@}*/

/*
 * Constants & macros for individual SIM_UIDMH bitfields
 */

/*!
 * @name Register SIM_UIDMH, field UID[31:0] (RO)
 *
 * Unique identification for the device.
 */
/*@{*/
#define BP_SIM_UIDMH_UID     (0U)          /*!< Bit position for SIM_UIDMH_UID. */
#define BM_SIM_UIDMH_UID     (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDMH_UID. */
#define BS_SIM_UIDMH_UID     (32U)         /*!< Bit field size in bits for SIM_UIDMH_UID. */

/*! @brief Read current value of the SIM_UIDMH_UID field. */
#define BR_SIM_UIDMH_UID(x)  (HW_SIM_UIDMH(x).U)
/*@}*/

/*******************************************************************************
 * HW_SIM_UIDML - Unique Identification Register Mid Low
 ******************************************************************************/

/*!
 * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_uidml
{
    uint32_t U;
    struct _hw_sim_uidml_bitfields
    {
        uint32_t UID : 32;             /*!< [31:0] Unique Identification */
    } B;
} hw_sim_uidml_t;

/*!
 * @name Constants and macros for entire SIM_UIDML register
 */
/*@{*/
#define HW_SIM_UIDML_ADDR(x)     ((x) + 0x105CU)

#define HW_SIM_UIDML(x)          (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR(x))
#define HW_SIM_UIDML_RD(x)       (HW_SIM_UIDML(x).U)
/*@}*/

/*
 * Constants & macros for individual SIM_UIDML bitfields
 */

/*!
 * @name Register SIM_UIDML, field UID[31:0] (RO)
 *
 * Unique identification for the device.
 */
/*@{*/
#define BP_SIM_UIDML_UID     (0U)          /*!< Bit position for SIM_UIDML_UID. */
#define BM_SIM_UIDML_UID     (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDML_UID. */
#define BS_SIM_UIDML_UID     (32U)         /*!< Bit field size in bits for SIM_UIDML_UID. */

/*! @brief Read current value of the SIM_UIDML_UID field. */
#define BR_SIM_UIDML_UID(x)  (HW_SIM_UIDML(x).U)
/*@}*/

/*******************************************************************************
 * HW_SIM_UIDL - Unique Identification Register Low
 ******************************************************************************/

/*!
 * @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_uidl
{
    uint32_t U;
    struct _hw_sim_uidl_bitfields
    {
        uint32_t UID : 32;             /*!< [31:0] Unique Identification */
    } B;
} hw_sim_uidl_t;

/*!
 * @name Constants and macros for entire SIM_UIDL register
 */
/*@{*/
#define HW_SIM_UIDL_ADDR(x)      ((x) + 0x1060U)

#define HW_SIM_UIDL(x)           (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR(x))
#define HW_SIM_UIDL_RD(x)        (HW_SIM_UIDL(x).U)
/*@}*/

/*
 * Constants & macros for individual SIM_UIDL bitfields
 */

/*!
 * @name Register SIM_UIDL, field UID[31:0] (RO)
 *
 * Unique identification for the device.
 */
/*@{*/
#define BP_SIM_UIDL_UID      (0U)          /*!< Bit position for SIM_UIDL_UID. */
#define BM_SIM_UIDL_UID      (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDL_UID. */
#define BS_SIM_UIDL_UID      (32U)         /*!< Bit field size in bits for SIM_UIDL_UID. */

/*! @brief Read current value of the SIM_UIDL_UID field. */
#define BR_SIM_UIDL_UID(x)   (HW_SIM_UIDL(x).U)
/*@}*/

/*******************************************************************************
 * HW_SIM_CLKDIV3 - System Clock Divider Register 3
 ******************************************************************************/

/*!
 * @brief HW_SIM_CLKDIV3 - System Clock Divider Register 3 (RW)
 *
 * Reset value: 0x00000000U
 *
 * The fraction created by this register must be <= 1.
 */
typedef union _hw_sim_clkdiv3
{
    uint32_t U;
    struct _hw_sim_clkdiv3_bitfields
    {
        uint32_t RESERVED0 : 8;        /*!< [7:0]  */
        uint32_t LCDCFRAC : 8;         /*!< [15:8] LCDCFRAC clock divider fraction. */
        uint32_t LCDCDIV : 12;         /*!< [27:16] LCDC Clock divder fraction */
        uint32_t RESERVED1 : 4;        /*!< [31:28]  */
    } B;
} hw_sim_clkdiv3_t;

/*!
 * @name Constants and macros for entire SIM_CLKDIV3 register
 */
/*@{*/
#define HW_SIM_CLKDIV3_ADDR(x)   ((x) + 0x1064U)

#define HW_SIM_CLKDIV3(x)        (*(__IO hw_sim_clkdiv3_t *) HW_SIM_CLKDIV3_ADDR(x))
#define HW_SIM_CLKDIV3_RD(x)     (HW_SIM_CLKDIV3(x).U)
#define HW_SIM_CLKDIV3_WR(x, v)  (HW_SIM_CLKDIV3(x).U = (v))
#define HW_SIM_CLKDIV3_SET(x, v) (HW_SIM_CLKDIV3_WR(x, HW_SIM_CLKDIV3_RD(x) |  (v)))
#define HW_SIM_CLKDIV3_CLR(x, v) (HW_SIM_CLKDIV3_WR(x, HW_SIM_CLKDIV3_RD(x) & ~(v)))
#define HW_SIM_CLKDIV3_TOG(x, v) (HW_SIM_CLKDIV3_WR(x, HW_SIM_CLKDIV3_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_CLKDIV3 bitfields
 */

/*!
 * @name Register SIM_CLKDIV3, field LCDCFRAC[15:8] (RW)
 *
 * This field sets the divide value for the fractional clock divider used as a
 * source for LCDC pixel clock. The source clock for the fractional clock divider
 * is set by the SOPT2 LCDCSRC[1:0] register bit. Divider output clock = Divider
 * input clock * ((LCDCFRAC+1)/(LCDCDIV+1))
 */
/*@{*/
#define BP_SIM_CLKDIV3_LCDCFRAC (8U)       /*!< Bit position for SIM_CLKDIV3_LCDCFRAC. */
#define BM_SIM_CLKDIV3_LCDCFRAC (0x0000FF00U) /*!< Bit mask for SIM_CLKDIV3_LCDCFRAC. */
#define BS_SIM_CLKDIV3_LCDCFRAC (8U)       /*!< Bit field size in bits for SIM_CLKDIV3_LCDCFRAC. */

/*! @brief Read current value of the SIM_CLKDIV3_LCDCFRAC field. */
#define BR_SIM_CLKDIV3_LCDCFRAC(x) (HW_SIM_CLKDIV3(x).B.LCDCFRAC)

/*! @brief Format value for bitfield SIM_CLKDIV3_LCDCFRAC. */
#define BF_SIM_CLKDIV3_LCDCFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV3_LCDCFRAC) & BM_SIM_CLKDIV3_LCDCFRAC)

/*! @brief Set the LCDCFRAC field to a new value. */
#define BW_SIM_CLKDIV3_LCDCFRAC(x, v) (HW_SIM_CLKDIV3_WR(x, (HW_SIM_CLKDIV3_RD(x) & ~BM_SIM_CLKDIV3_LCDCFRAC) | BF_SIM_CLKDIV3_LCDCFRAC(v)))
/*@}*/

/*!
 * @name Register SIM_CLKDIV3, field LCDCDIV[27:16] (RW)
 *
 * This field sets the fraction multiply value for the fractional clock divider
 * used as a source for LCDC pixel clock. The source clock for the fractional
 * clock divider is set by the SOPT2 LCDCSRC[1:0] register bit. Divider output clock
 * = Divider input clock*((LCDCFRAC+1)/(LCDCDIV+1))
 */
/*@{*/
#define BP_SIM_CLKDIV3_LCDCDIV (16U)       /*!< Bit position for SIM_CLKDIV3_LCDCDIV. */
#define BM_SIM_CLKDIV3_LCDCDIV (0x0FFF0000U) /*!< Bit mask for SIM_CLKDIV3_LCDCDIV. */
#define BS_SIM_CLKDIV3_LCDCDIV (12U)       /*!< Bit field size in bits for SIM_CLKDIV3_LCDCDIV. */

/*! @brief Read current value of the SIM_CLKDIV3_LCDCDIV field. */
#define BR_SIM_CLKDIV3_LCDCDIV(x) (HW_SIM_CLKDIV3(x).B.LCDCDIV)

/*! @brief Format value for bitfield SIM_CLKDIV3_LCDCDIV. */
#define BF_SIM_CLKDIV3_LCDCDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV3_LCDCDIV) & BM_SIM_CLKDIV3_LCDCDIV)

/*! @brief Set the LCDCDIV field to a new value. */
#define BW_SIM_CLKDIV3_LCDCDIV(x, v) (HW_SIM_CLKDIV3_WR(x, (HW_SIM_CLKDIV3_RD(x) & ~BM_SIM_CLKDIV3_LCDCDIV) | BF_SIM_CLKDIV3_LCDCDIV(v)))
/*@}*/

/*******************************************************************************
 * HW_SIM_CLKDIV4 - System Clock Divider Register 4
 ******************************************************************************/

/*!
 * @brief HW_SIM_CLKDIV4 - System Clock Divider Register 4 (RW)
 *
 * Reset value: 0x00000002U
 */
typedef union _hw_sim_clkdiv4
{
    uint32_t U;
    struct _hw_sim_clkdiv4_bitfields
    {
        uint32_t TRACEFRAC : 1;        /*!< [0] Trace clock divider fraction */
        uint32_t TRACEDIV : 3;         /*!< [3:1] Trace clock divider divisor */
        uint32_t RESERVED0 : 20;       /*!< [23:4]  */
        uint32_t NFCFRAC : 3;          /*!< [26:24] NFC clock divider fraction */
        uint32_t NFCDIV : 5;           /*!< [31:27] NFC clock divider divisor */
    } B;
} hw_sim_clkdiv4_t;

/*!
 * @name Constants and macros for entire SIM_CLKDIV4 register
 */
/*@{*/
#define HW_SIM_CLKDIV4_ADDR(x)   ((x) + 0x1068U)

#define HW_SIM_CLKDIV4(x)        (*(__IO hw_sim_clkdiv4_t *) HW_SIM_CLKDIV4_ADDR(x))
#define HW_SIM_CLKDIV4_RD(x)     (HW_SIM_CLKDIV4(x).U)
#define HW_SIM_CLKDIV4_WR(x, v)  (HW_SIM_CLKDIV4(x).U = (v))
#define HW_SIM_CLKDIV4_SET(x, v) (HW_SIM_CLKDIV4_WR(x, HW_SIM_CLKDIV4_RD(x) |  (v)))
#define HW_SIM_CLKDIV4_CLR(x, v) (HW_SIM_CLKDIV4_WR(x, HW_SIM_CLKDIV4_RD(x) & ~(v)))
#define HW_SIM_CLKDIV4_TOG(x, v) (HW_SIM_CLKDIV4_WR(x, HW_SIM_CLKDIV4_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_CLKDIV4 bitfields
 */

/*!
 * @name Register SIM_CLKDIV4, field TRACEFRAC[0] (RW)
 *
 * This field sets the divide value for the fractional clock divider used as a
 * source for trace clock. The source clock for the fractional clock divider is
 * set by the SOPT2 TRACECLKSEL register bit. Divider output clock = Divider input
 * clock*((TRACEFRAC+1)/(TRACEDIV+1))
 */
/*@{*/
#define BP_SIM_CLKDIV4_TRACEFRAC (0U)      /*!< Bit position for SIM_CLKDIV4_TRACEFRAC. */
#define BM_SIM_CLKDIV4_TRACEFRAC (0x00000001U) /*!< Bit mask for SIM_CLKDIV4_TRACEFRAC. */
#define BS_SIM_CLKDIV4_TRACEFRAC (1U)      /*!< Bit field size in bits for SIM_CLKDIV4_TRACEFRAC. */

/*! @brief Read current value of the SIM_CLKDIV4_TRACEFRAC field. */
#define BR_SIM_CLKDIV4_TRACEFRAC(x) (BITBAND_ACCESS32(HW_SIM_CLKDIV4_ADDR(x), BP_SIM_CLKDIV4_TRACEFRAC))

/*! @brief Format value for bitfield SIM_CLKDIV4_TRACEFRAC. */
#define BF_SIM_CLKDIV4_TRACEFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV4_TRACEFRAC) & BM_SIM_CLKDIV4_TRACEFRAC)

/*! @brief Set the TRACEFRAC field to a new value. */
#define BW_SIM_CLKDIV4_TRACEFRAC(x, v) (BITBAND_ACCESS32(HW_SIM_CLKDIV4_ADDR(x), BP_SIM_CLKDIV4_TRACEFRAC) = (v))
/*@}*/

/*!
 * @name Register SIM_CLKDIV4, field TRACEDIV[3:1] (RW)
 *
 * This field sets the divide value for the fractional clock divider used as a
 * source for trace clock. The source clock for the fractional clock divider is
 * set by the SOPT2 TRACECLKSEL register bit. Divider output clock = Divider input
 * clock * ((TRACEFRAC+1)/(TRACEDIV+1))
 */
/*@{*/
#define BP_SIM_CLKDIV4_TRACEDIV (1U)       /*!< Bit position for SIM_CLKDIV4_TRACEDIV. */
#define BM_SIM_CLKDIV4_TRACEDIV (0x0000000EU) /*!< Bit mask for SIM_CLKDIV4_TRACEDIV. */
#define BS_SIM_CLKDIV4_TRACEDIV (3U)       /*!< Bit field size in bits for SIM_CLKDIV4_TRACEDIV. */

/*! @brief Read current value of the SIM_CLKDIV4_TRACEDIV field. */
#define BR_SIM_CLKDIV4_TRACEDIV(x) (HW_SIM_CLKDIV4(x).B.TRACEDIV)

/*! @brief Format value for bitfield SIM_CLKDIV4_TRACEDIV. */
#define BF_SIM_CLKDIV4_TRACEDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV4_TRACEDIV) & BM_SIM_CLKDIV4_TRACEDIV)

/*! @brief Set the TRACEDIV field to a new value. */
#define BW_SIM_CLKDIV4_TRACEDIV(x, v) (HW_SIM_CLKDIV4_WR(x, (HW_SIM_CLKDIV4_RD(x) & ~BM_SIM_CLKDIV4_TRACEDIV) | BF_SIM_CLKDIV4_TRACEDIV(v)))
/*@}*/

/*!
 * @name Register SIM_CLKDIV4, field NFCFRAC[26:24] (RW)
 *
 * This field sets the fraction multiply value for the fractional clock divider
 * used as a source for NFC flash clock. The source clock for the fractional
 * clock divider is set by the SOPT2[NFCSRC] bitfield. Divider output clock = Divider
 * input clock x ((NFCFRAC+1)/(NFCDIV+1)) The reciprocal of
 * ((NFCFRAC+1)/(NFCDIV+1)) must be a multiple of 0.5. For example, NFCFRAC = 1 and NFCDIV = 2 is a
 * valid setting, since the reciprocal is 1.5. However, NFCFRAC = 2 and NFCDIV=7
 * is not a valid setting, since the reciprocal is 2.6667.
 */
/*@{*/
#define BP_SIM_CLKDIV4_NFCFRAC (24U)       /*!< Bit position for SIM_CLKDIV4_NFCFRAC. */
#define BM_SIM_CLKDIV4_NFCFRAC (0x07000000U) /*!< Bit mask for SIM_CLKDIV4_NFCFRAC. */
#define BS_SIM_CLKDIV4_NFCFRAC (3U)        /*!< Bit field size in bits for SIM_CLKDIV4_NFCFRAC. */

/*! @brief Read current value of the SIM_CLKDIV4_NFCFRAC field. */
#define BR_SIM_CLKDIV4_NFCFRAC(x) (HW_SIM_CLKDIV4(x).B.NFCFRAC)

/*! @brief Format value for bitfield SIM_CLKDIV4_NFCFRAC. */
#define BF_SIM_CLKDIV4_NFCFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV4_NFCFRAC) & BM_SIM_CLKDIV4_NFCFRAC)

/*! @brief Set the NFCFRAC field to a new value. */
#define BW_SIM_CLKDIV4_NFCFRAC(x, v) (HW_SIM_CLKDIV4_WR(x, (HW_SIM_CLKDIV4_RD(x) & ~BM_SIM_CLKDIV4_NFCFRAC) | BF_SIM_CLKDIV4_NFCFRAC(v)))
/*@}*/

/*!
 * @name Register SIM_CLKDIV4, field NFCDIV[31:27] (RW)
 *
 * This field sets the divide value for the fractional clock divider used as a
 * source for NFC flash clock. The source clock for the fractional clock divider
 * is set by the SOPT2[NFCSRC] bitfield. Divider output clock = Divider input
 * clock x ((NFCFRAC+1)/(NFCDIV+1)) The reciprocal of ((NFCFRAC+1)/(NFCDIV+1)) must
 * be a multiple of 0.5. For example, NFCFRAC = 1 and NFCDIV = 2 is a valid
 * setting, since the reciprocal is 1.5. However, NFCFRAC = 2 and NFCDIV=7 is not a
 * valid setting, since the reciprocal is 2.6667.
 */
/*@{*/
#define BP_SIM_CLKDIV4_NFCDIV (27U)        /*!< Bit position for SIM_CLKDIV4_NFCDIV. */
#define BM_SIM_CLKDIV4_NFCDIV (0xF8000000U) /*!< Bit mask for SIM_CLKDIV4_NFCDIV. */
#define BS_SIM_CLKDIV4_NFCDIV (5U)         /*!< Bit field size in bits for SIM_CLKDIV4_NFCDIV. */

/*! @brief Read current value of the SIM_CLKDIV4_NFCDIV field. */
#define BR_SIM_CLKDIV4_NFCDIV(x) (HW_SIM_CLKDIV4(x).B.NFCDIV)

/*! @brief Format value for bitfield SIM_CLKDIV4_NFCDIV. */
#define BF_SIM_CLKDIV4_NFCDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV4_NFCDIV) & BM_SIM_CLKDIV4_NFCDIV)

/*! @brief Set the NFCDIV field to a new value. */
#define BW_SIM_CLKDIV4_NFCDIV(x, v) (HW_SIM_CLKDIV4_WR(x, (HW_SIM_CLKDIV4_RD(x) & ~BM_SIM_CLKDIV4_NFCDIV) | BF_SIM_CLKDIV4_NFCDIV(v)))
/*@}*/

/*******************************************************************************
 * HW_SIM_MCR - Misc Control Register
 ******************************************************************************/

/*!
 * @brief HW_SIM_MCR - Misc Control Register (RW)
 *
 * Reset value: 0x00000000U
 */
typedef union _hw_sim_mcr
{
    uint32_t U;
    struct _hw_sim_mcr_bitfields
    {
        uint32_t RESERVED0 : 16;       /*!< [15:0]  */
        uint32_t LCDSTART : 1;         /*!< [16] Start LCDC display */
        uint32_t RESERVED1 : 12;       /*!< [28:17]  */
        uint32_t PDBLOOP : 1;          /*!< [29] PDB Loop Mode */
        uint32_t ULPICLKOBE : 1;       /*!< [30] 60 MHz ULPI clock (ULPI_CLK)
                                        * output enable */
        uint32_t TRACECLKDIS : 1;      /*!< [31] Trace clock disable. */
    } B;
} hw_sim_mcr_t;

/*!
 * @name Constants and macros for entire SIM_MCR register
 */
/*@{*/
#define HW_SIM_MCR_ADDR(x)       ((x) + 0x106CU)

#define HW_SIM_MCR(x)            (*(__IO hw_sim_mcr_t *) HW_SIM_MCR_ADDR(x))
#define HW_SIM_MCR_RD(x)         (HW_SIM_MCR(x).U)
#define HW_SIM_MCR_WR(x, v)      (HW_SIM_MCR(x).U = (v))
#define HW_SIM_MCR_SET(x, v)     (HW_SIM_MCR_WR(x, HW_SIM_MCR_RD(x) |  (v)))
#define HW_SIM_MCR_CLR(x, v)     (HW_SIM_MCR_WR(x, HW_SIM_MCR_RD(x) & ~(v)))
#define HW_SIM_MCR_TOG(x, v)     (HW_SIM_MCR_WR(x, HW_SIM_MCR_RD(x) ^  (v)))
/*@}*/

/*
 * Constants & macros for individual SIM_MCR bitfields
 */

/*!
 * @name Register SIM_MCR, field LCDSTART[16] (RW)
 *
 * The LCDC starts from beginning of the frame when this bit is set.
 *
 * Values:
 * - 0 - Stops LCDC display
 * - 1 - Starts LCDC display
 */
/*@{*/
#define BP_SIM_MCR_LCDSTART  (16U)         /*!< Bit position for SIM_MCR_LCDSTART. */
#define BM_SIM_MCR_LCDSTART  (0x00010000U) /*!< Bit mask for SIM_MCR_LCDSTART. */
#define BS_SIM_MCR_LCDSTART  (1U)          /*!< Bit field size in bits for SIM_MCR_LCDSTART. */

/*! @brief Read current value of the SIM_MCR_LCDSTART field. */
#define BR_SIM_MCR_LCDSTART(x) (BITBAND_ACCESS32(HW_SIM_MCR_ADDR(x), BP_SIM_MCR_LCDSTART))

/*! @brief Format value for bitfield SIM_MCR_LCDSTART. */
#define BF_SIM_MCR_LCDSTART(v) ((uint32_t)((uint32_t)(v) << BP_SIM_MCR_LCDSTART) & BM_SIM_MCR_LCDSTART)

/*! @brief Set the LCDSTART field to a new value. */
#define BW_SIM_MCR_LCDSTART(x, v) (BITBAND_ACCESS32(HW_SIM_MCR_ADDR(x), BP_SIM_MCR_LCDSTART) = (v))
/*@}*/

/*!
 * @name Register SIM_MCR, field PDBLOOP[29] (RW)
 *
 * Values:
 * - 0 - Provides two seperated minor loop, loop for ADC0/1 and loop for ADC2/3D
 * - 1 - Provides a loop to involve ADC0, ADC1, ADC2 and ADC3.
 */
/*@{*/
#define BP_SIM_MCR_PDBLOOP   (29U)         /*!< Bit position for SIM_MCR_PDBLOOP. */
#define BM_SIM_MCR_PDBLOOP   (0x20000000U) /*!< Bit mask for SIM_MCR_PDBLOOP. */
#define BS_SIM_MCR_PDBLOOP   (1U)          /*!< Bit field size in bits for SIM_MCR_PDBLOOP. */

/*! @brief Read current value of the SIM_MCR_PDBLOOP field. */
#define BR_SIM_MCR_PDBLOOP(x) (BITBAND_ACCESS32(HW_SIM_MCR_ADDR(x), BP_SIM_MCR_PDBLOOP))

/*! @brief Format value for bitfield SIM_MCR_PDBLOOP. */
#define BF_SIM_MCR_PDBLOOP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_MCR_PDBLOOP) & BM_SIM_MCR_PDBLOOP)

/*! @brief Set the PDBLOOP field to a new value. */
#define BW_SIM_MCR_PDBLOOP(x, v) (BITBAND_ACCESS32(HW_SIM_MCR_ADDR(x), BP_SIM_MCR_PDBLOOP) = (v))
/*@}*/

/*!
 * @name Register SIM_MCR, field ULPICLKOBE[30] (RW)
 *
 * Values:
 * - 0 - Internal generated 60MHz ULPI clock is not output to the ULPI_CLK pin.
 * - 1 - Interanl generated 60MHz ULPI clock provide clock for external ULPI phy.
 */
/*@{*/
#define BP_SIM_MCR_ULPICLKOBE (30U)        /*!< Bit position for SIM_MCR_ULPICLKOBE. */
#define BM_SIM_MCR_ULPICLKOBE (0x40000000U) /*!< Bit mask for SIM_MCR_ULPICLKOBE. */
#define BS_SIM_MCR_ULPICLKOBE (1U)         /*!< Bit field size in bits for SIM_MCR_ULPICLKOBE. */

/*! @brief Read current value of the SIM_MCR_ULPICLKOBE field. */
#define BR_SIM_MCR_ULPICLKOBE(x) (BITBAND_ACCESS32(HW_SIM_MCR_ADDR(x), BP_SIM_MCR_ULPICLKOBE))

/*! @brief Format value for bitfield SIM_MCR_ULPICLKOBE. */
#define BF_SIM_MCR_ULPICLKOBE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_MCR_ULPICLKOBE) & BM_SIM_MCR_ULPICLKOBE)

/*! @brief Set the ULPICLKOBE field to a new value. */
#define BW_SIM_MCR_ULPICLKOBE(x, v) (BITBAND_ACCESS32(HW_SIM_MCR_ADDR(x), BP_SIM_MCR_ULPICLKOBE) = (v))
/*@}*/

/*!
 * @name Register SIM_MCR, field TRACECLKDIS[31] (RW)
 *
 * Values:
 * - 0 - Enables trace clock.
 * - 1 - Disable trace clock.
 */
/*@{*/
#define BP_SIM_MCR_TRACECLKDIS (31U)       /*!< Bit position for SIM_MCR_TRACECLKDIS. */
#define BM_SIM_MCR_TRACECLKDIS (0x80000000U) /*!< Bit mask for SIM_MCR_TRACECLKDIS. */
#define BS_SIM_MCR_TRACECLKDIS (1U)        /*!< Bit field size in bits for SIM_MCR_TRACECLKDIS. */

/*! @brief Read current value of the SIM_MCR_TRACECLKDIS field. */
#define BR_SIM_MCR_TRACECLKDIS(x) (BITBAND_ACCESS32(HW_SIM_MCR_ADDR(x), BP_SIM_MCR_TRACECLKDIS))

/*! @brief Format value for bitfield SIM_MCR_TRACECLKDIS. */
#define BF_SIM_MCR_TRACECLKDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_MCR_TRACECLKDIS) & BM_SIM_MCR_TRACECLKDIS)

/*! @brief Set the TRACECLKDIS field to a new value. */
#define BW_SIM_MCR_TRACECLKDIS(x, v) (BITBAND_ACCESS32(HW_SIM_MCR_ADDR(x), BP_SIM_MCR_TRACECLKDIS) = (v))
/*@}*/

/*******************************************************************************
 * hw_sim_t - module struct
 ******************************************************************************/
/*!
 * @brief All SIM module registers.
 */
#pragma pack(1)
typedef struct _hw_sim
{
    __IO hw_sim_sopt1_t SOPT1;             /*!< [0x0] System Options Register 1 */
    __IO hw_sim_sopt1cfg_t SOPT1CFG;       /*!< [0x4] SOPT1 Configuration Register */
    uint8_t _reserved0[4092];
    __IO hw_sim_sopt2_t SOPT2;             /*!< [0x1004] System Options Register 2 */
    uint8_t _reserved1[4];
    __IO hw_sim_sopt4_t SOPT4;             /*!< [0x100C] System Options Register 4 */
    __IO hw_sim_sopt5_t SOPT5;             /*!< [0x1010] System Options Register 5 */
    __IO hw_sim_sopt6_t SOPT6;             /*!< [0x1014] System Options Register 6 */
    __IO hw_sim_sopt7_t SOPT7;             /*!< [0x1018] System Options Register 7 */
    uint8_t _reserved2[8];
    __I hw_sim_sdid_t SDID;                /*!< [0x1024] System Device Identification Register */
    __IO hw_sim_scgc1_t SCGC1;             /*!< [0x1028] System Clock Gating Control Register 1 */
    __IO hw_sim_scgc2_t SCGC2;             /*!< [0x102C] System Clock Gating Control Register 2 */
    __IO hw_sim_scgc3_t SCGC3;             /*!< [0x1030] System Clock Gating Control Register 3 */
    __IO hw_sim_scgc4_t SCGC4;             /*!< [0x1034] System Clock Gating Control Register 4 */
    __IO hw_sim_scgc5_t SCGC5;             /*!< [0x1038] System Clock Gating Control Register 5 */
    __IO hw_sim_scgc6_t SCGC6;             /*!< [0x103C] System Clock Gating Control Register 6 */
    __IO hw_sim_scgc7_t SCGC7;             /*!< [0x1040] System Clock Gating Control Register 7 */
    __IO hw_sim_clkdiv1_t CLKDIV1;         /*!< [0x1044] System Clock Divider Register 1 */
    __IO hw_sim_clkdiv2_t CLKDIV2;         /*!< [0x1048] System Clock Divider Register 2 */
    __IO hw_sim_fcfg1_t FCFG1;             /*!< [0x104C] Flash Configuration Register 1 */
    __I hw_sim_fcfg2_t FCFG2;              /*!< [0x1050] Flash Configuration Register 2 */
    __I hw_sim_uidh_t UIDH;                /*!< [0x1054] Unique Identification Register High */
    __I hw_sim_uidmh_t UIDMH;              /*!< [0x1058] Unique Identification Register Mid-High */
    __I hw_sim_uidml_t UIDML;              /*!< [0x105C] Unique Identification Register Mid Low */
    __I hw_sim_uidl_t UIDL;                /*!< [0x1060] Unique Identification Register Low */
    __IO hw_sim_clkdiv3_t CLKDIV3;         /*!< [0x1064] System Clock Divider Register 3 */
    __IO hw_sim_clkdiv4_t CLKDIV4;         /*!< [0x1068] System Clock Divider Register 4 */
    __IO hw_sim_mcr_t MCR;                 /*!< [0x106C] Misc Control Register */
} hw_sim_t;
#pragma pack()

/*! @brief Macro to access all SIM registers. */
/*! @param x SIM module instance base address. */
/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 *     use the '&' operator, like <code>&HW_SIM(SIM_BASE)</code>. */
#define HW_SIM(x)      (*(hw_sim_t *)(x))

#endif /* __HW_SIM_REGISTERS_H__ */
/* v33/140401/2.1.0 */
/* EOF */
